Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions1,2. This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing3,4. By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip'1,6-8. As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge10,11, this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

Cubic-wavelength mode volume photonic crystal nanobeam cavities in a monolithic CMOS platform.

We report on the design, fabrication, and experimental characterization of photonic crystal (PhC) nanobeam cavities with the smallest footprint, largest intrinsic quality factor, and smallest mode volume to be demonstrated to date in a monolithic CMOS platform. Two types of cavities were designed, with opposite spatial mode symmetries. The opposite mode symmetry, combined with evanescent coupling, allows the nanobeam cavities to be used in reflectionless topologies, desirable in complex photonic integrated circuits (PICs). The devices were implemented and fabricated in a 45 nm monolithic electronics-photonics CMOS platform optimized for silicon photonics (GlobalFoundries 45CLO) and do not require any post-processing. Quality factors exceeding 100 000 were measured for both devices, the highest, to the best of our knowledge, among fully cladded PhC nanobeam cavities in any silicon-on-insulator (SOI) platform. Additionally, the ability of the cavities to confine light into small mode volumes, of the order of (λ/n)3, was confirmed experimentally using near-field scanning optical microscopy (NSOM). These types of cavities are an important step toward realizing ultra-low energy active devices required for the next generation of integrated optical links beyond the current microring resonator-based links and other CMOS PICs.

Vernier optical phased array lidar transceivers.

Optical phased arrays (OPAs) which beam-steer in two dimensions (2D) are currently limited to grating row spacings well above a half wavelength. This gives rise to grating lobes along one axis which limit the field of view (FOV), introduce return signal ambiguity, and reduce the optical efficiency in lidar applications. We demonstrate a Vernier transceiver scheme which uses paired transmit and receive phased arrays with different row periodicities, leading to mismatched grating lobe angular spacings and only a single aligned pair of transmit and receive lobes. This permits a return signal from a target in the desired lobe to be efficiently coupled back into the receive OPA while back-scatter from the other grating lobes is rejected, removing the ambiguity. Our proposal goes beyond previously considered Vernier schemes in other domains like RF and sound, to enable a dynamic Vernier where all beam directions are simultaneously Vernier aligned, and allow ultra-fast scanning, or multi-beam, operation with Vernier lobe suppression. We analyze two variants of grating lobe suppressing beam-steering configurations, one of which eliminates the FOV limitation, and find the conditions for optimal lobe suppression. We present the first, to the best of our knowledge, experimental demonstration of an OPA Vernier transceiver, including grating lobe suppression of 6.4 dB and beam steering across 5.5°. The demonstration is based on a pair of 2D-wavelength-steered serpentine OPAs. These results address the pervasive issue of grating lobes in integrated photonic lidar schemes, opening the way to larger FOVs and reduced complexity 2D beam-steering designs.

Polarization-insensitive 1D grating coupler based on a zero-birefringence subwavelength corelet waveguide.

Grating coupler devices provide efficient, foundry-compatible vertical fiber-to-chip coupling solutions in integrated photonic platforms. However, standard grating coupler designs are highly polarization sensitive, which hinders their adoption. We present a new, to the best of our knowledge, type of 1D polarization-insensitive grating coupler (PIGC) that is based on a zero-birefringence subwavelength "corelet" waveguide. We demonstrate a PIGC for coupling in the telecommunications O-band in a 45-nm-node monolithic silicon-on-insulator (SOI) CMOS electronic-photonic platform, with measured insertion losses of 6.7 and 6.1 dB to transverse electric and transverse magnetic polarizations, respectively, and a ±1-dB polarization dependent loss bandwidth of 73 nm.

Reflectionless dual standing-wave microcavity resonator units for photonic integrated circuits.

We propose a novel photonic circuit element configuration that emulates the through-port response of a bus coupled traveling-wave resonator using two standing-wave resonant cavities. In this "reflectionless resonator unit", the two constituent cavities, here photonic crystal (PhC) nanobeams, exhibit opposite mode symmetries and may otherwise belong to a single design family. They are coupled evanescently to the bus waveguide without mutual coupling. We show theoretically, and verify using FDTD simulations, that reflection is eliminated when the two cavities are wavelength aligned. This occurs due to symmetry-induced destructive interference at the bus coupling region in the proposed photonic circuit topology. The transmission is equivalent to that of a bus-coupled traveling-wave (e.g. microring) resonator for all coupling conditions. We experimentally demonstrate an implementation fabricated in a new 45 nm silicon-on-insulator complementary metal-oxide semiconductor (SOI CMOS) electronic-photonic process. Both PhC nanobeam cavities have a full-width half-maximum (FWHM) mode length of 4.28 µm and measured intrinsic Q's in excess of 200,000. When the resonances are tuned to degeneracy and coalesce, transmission dips of the over-coupled PhC nanobeam cavities of -16 dB and -17 dB nearly disappear showing a remaining single dip of -4.2 dB, while reflection peaks are simultaneously reduced by 10 dB, demonstrating the quasi-traveling-wave behavior. This photonic circuit topology paves the way for realizing low-energy active devices such as modulators and detectors that can be cascaded to form wavelength-division multiplexed links with smaller power consumption and footprint than traveling wave, ring resonator based implementations.

Compact multi-million Q resonators and 100 MHz passband filter bank in a thick-SOI photonics platform.

We demonstrate ring and racetrack resonators with Qs of 3.8 to 7.5 million and 100 MHz bandwidth racetrack resonator filters, implemented in a thick silicon-on-insulator foundry platform that features a 3 µm thick device layer. We show that special racetrack resonators (with weakly guiding straight sections that transition to strongly confining bends) implemented in this platform can be preferable to rings for applications such as integrated microwave-photonic signal processing that require filters with sub-GHz bandwidth, tens of GHz of free spectral range (FSR), and a compact footprint for dense system-on-chip integration. We demonstrate ring resonators with 7.5×106 intrinsic Q, but limited FSR of 5.1 GHz and a taxing footprint of 21mm2 due to a large 2.6 mm bend-loss-limited radius. In comparison, we demonstrate two racetrack resonator designs with intrinsic Qs of 3.8×106 and 4.3×106, larger respective FSRs of 11.6 GHz and 7.9 GHz, and less than 1/20th the area of the ring resonator. Using racetrack resonators, we implemented a four-channel, 100 MHz wide passband filter bank with 4.2 to 5.4 dB insertion loss to drop ports.

Gradient-index optical fiber lens for efficient fiber-to-chip coupling.

A gradient-index optical fiber lens is proposed and fabricated on the tip of a single-mode fiber using focused ion beam milling. Second-order effective medium theory is used to design a gradual change in the fill factor, which ensures a parabolic effective refractive index distribution. The proposed fiber lens design is simulated via the three-dimensional finite-difference time-domain method, and demonstrated through confocal optical measurements. At a wavelength of 1550 nm, the fabricated lenses focus a 10.4 µm mode field diameter exiting the fiber into spot sizes between 3-5 µm, located 4-6 µm away from the fiber tip. Direct coupling into a silicon-on-insulator chip is also demonstrated, where the fabricated gradient-index lens has a coupling efficiency comparable to a commercial lensed fiber.

Silicon photonic time-wavelength pulse interleaver for photonic analog-to-digital converters.

A 4-channel time-wavelength optical pulse interleaver is implemented on a silicon chip. The interleaver forms a train of pulses with periodically changing wavelengths by demultiplexing the input pulse train into several wavelength components, delaying these components with respect to each other, and multiplexing them back into a single path. The interleaver is integrated on a silicon chip, with two arrays of microring resonator filters performing multiplexing and demultiplexing, and long sections of silicon waveguides acting as delay lines. The 4-channel interleaver is designed for an input pulse train with 1 GHz repetition rate, and is measured to have 0.35% RMS pulse timing error, insertion loss between 1.6 dB and 5.8 dB in different channels, crosstalk below -24 dB, and 52 nm free spectral range achieved using the Vernier effect.