Plasma-enhanced atomic layer deposition of Sn-doped indium oxide semiconductor nano-films for thin-film transistors.

Sn-doped indium oxide (ITO) semiconductor nano-films are fabricated by plasma-enhanced atomic layer deposition using trimethylindium (TMIn), tetrakis(dimethylamino)tin (TDMASn), and O2plasma as the sources of In, Sn and O, respectively. A shared temperature window of 150 °C- 200 °C is observed for the deposition of ITO nano-films. The introduction of Sn into indium oxide is found to increase the concentration of oxygen into the ITO films and inhibit crystallization. Furthermore, two oxidation states are observed for In and Sn, respectively. With the increment of interfaces of In-O/Sn-O in the ITO films, the relative percentage of In3+ions increases and that of Sn4+decreases, which is generated by interfacial competing reactions. By optimizing the channel component, the In0.77Sn0.23O1.11thin-film transistors (TFTs) demonstrate high performance, includingµFEof 52.7 cm2V-1s-1, and a highION/IOFFof ∼5 × 109. Moreover, the devices show excellent positive bias temperature stress stability at 3 MV cm-1and 85 °C, i.e. a minimalVthshift of 0.017 V after 4 ks stress. This work highlights the successful application of ITO semiconductor nano-films by ALD for TFTs.

Performance improvement of Hf0.45Zr0.55Oxferroelectric field effect transistor memory with ultrathin Al-O bonds-modified InOxchannels.

Ferroelectric field effect transistor (FeFET) memories with hafnium zirconium oxide (HZO) ferroelectric gate dielectric and ultrathin InOxchannel exhibit promising applicability in monolithic three-dimensional (M3D) integrated chips. However, the inferior stability of the devices severely limits their applications. In this work, we studied the effect of single cycle of atomic-layer-deposited Al-O bonds repeatedly embedded into an ultrathin InOxchannel (∼2.8 nm) on the Hf0.45Zr0.55OxFeFET memory performance. Compared to the pure InOxchannel, three cycles of Al-O bonds modified InOxchannel (IAO-3) generates a much larger memory window (i.e. drain current ratio between the programmed and erased devices) under the same program conditions (+5.5 V/500 ns), especially after post-annealing at 325 °C for 180 s in O2(1238 versus 317). Meanwhile, the annealed IAO-3 FeFET memory also shows quite stable data retention up to 104s, and much more robust program/erase stabilities till 105cycles. This is because the modification of strong Al-O bonds stabilizes the oxygen vacancies and reduces the bulk trap density in the channel. Furthermore, it is indicated that the program and erase efficiencies increase gradually with reducing the channel length of the memory device. By demonstrating markedly improved performance of the HZO FeFET memory with the ultrathin IAO-3 channel, this work provides a promising device for M3D integratable logic and memory convergent systems.

A Study on the Harmonic Distortion of Seismic-Grade Sigma-Delta MEMS Accelerometers Using a Multiple Degree-of-Freedom Model.

Harmonic distortion is one of the dominant factors limiting the overall signal-to-noise and distortion ratio of seismic-grade sigma-delta MEMS accelerometers. This study investigates harmonic distortion based on the multiple degree-of-freedom model (MDM) established in our previous study. The main advantage of using an MDM is that the effect of finger flexibility on harmonic distortion is considered. Initially, the nonlinear relationship between the input acceleration and output signal is derived using the MDM. Then, harmonic distortion is simulated and described in terms of the nonlinear input-output relationship. It is found that finger flexibility and parasitic capacitance mismatch both decrease harmonic distortion. Finally, the experimental testing of harmonic distortion is implemented. By reducing the finger length to realize a higher stiffness and compensating for the parasitic capacitance mismatch, the total harmonic distortion decreases from -66.8 dB to -86.9 dB.

Multiple-Degree-of-Freedom Modeling and Simulation for Seismic-Grade Sigma-Delta MEMS Capacitive Accelerometers.

The high-order mechanical resonances of the sensing element in a high-vacuum environment can significantly degrade the noise and distortion performance of seismic-grade sigma-delta MEMS capacitive accelerometers. However, the current modeling approach is unable to evaluate the effects of high-order mechanical resonances. This study proposes a novel multiple-degree-of-freedom (MDOF) model to evaluate the noise and distortion induced by high-order mechanical resonances. Firstly, the MDOF dynamic equations of the sensing element are derived using the principle of modal superposition and Lagrange's equations. Secondly, a fifth-order electromechanical sigma-delta system of the MEMS accelerometer is established in Simulink based on the dynamic equations of the sensing element. Then, the mechanism through which the high-order mechanical resonances degrade the noise and distortion performances is discovered by analyzing the simulated result. Finally, a noise and distortion suppression method is proposed based on the appropriate improvement in high-order natural frequency. The results show that the low-frequency noise drastically decreases from about -120.5 dB to -175.3 dB after the high-order natural frequency increases from about 130 kHz to 455 kHz. The harmonic distortion also reduces significantly.

MRI-based brain tumor segmentation using FPGA-accelerated neural network.

BACKGROUND: Brain tumor segmentation is a challenging problem in medical image processing and analysis. It is a very time-consuming and error-prone task. In order to reduce the burden on physicians and improve the segmentation accuracy, the computer-aided detection (CAD) systems need to be developed. Due to the powerful feature learning ability of the deep learning technology, many deep learning-based methods have been applied to the brain tumor segmentation CAD systems and achieved satisfactory accuracy. However, deep learning neural networks have high computational complexity, and the brain tumor segmentation process consumes significant time. Therefore, in order to achieve the high segmentation accuracy of brain tumors and obtain the segmentation results efficiently, it is very demanding to speed up the segmentation process of brain tumors. RESULTS: Compared with traditional computing platforms, the proposed FPGA accelerator has greatly improved the speed and the power consumption. Based on the BraTS19 and BraTS20 dataset, our FPGA-based brain tumor segmentation accelerator is 5.21 and 44.47 times faster than the TITAN V GPU and the Xeon CPU. In addition, by comparing energy efficiency, our design can achieve 11.22 and 82.33 times energy efficiency than GPU and CPU, respectively. CONCLUSION: We quantize and retrain the neural network for brain tumor segmentation and merge batch normalization layers to reduce the parameter size and computational complexity. The FPGA-based brain tumor segmentation accelerator is designed to map the quantized neural network model. The accelerator can increase the segmentation speed and reduce the power consumption on the basis of ensuring high accuracy which provides a new direction for the automatic segmentation and remote diagnosis of brain tumors.

Flexible and Filter-Free Color-Imaging Sensors with Multicomponent Perovskites Deposited Using Enhanced Vapor Technology.

Halide perovskites are promising photoactive materials for filter-free color-imaging sensors owing to their outstanding optoelectronic properties, tunable bandgaps, and suitability for large-scale fabrication. However, producing patterned perovskite films of sufficiently high quality for such applications poses a challenge for existing fabrication methods: using solution processes to prepare patterned perovskite films is complicated, while evaporation methods often result in perovskite photodetectors with limited performance. In this paper, the authors report the development of an improved evaporation method in which substrates are treated with a brominated (3-aminopropyl) triethoxysilane self-assembled monolayer to improve the properties of the patterned perovskite films. The resulting perovskite photodetectors exhibit significantly enhanced photosensitivity and long-term stability (exceeding 100 days). Additionally, the polymer substrates facilitate device flexibility. Finally, perovskites comprising three different halide components, each with a different bandgap, are integrated into a device array using the developed evaporation technology, yielding sensors that enable the discrimination of red, green, and blue colors. Thus, the flexible photosensor arrays can generate colorful images closely resembling perceived patterns, demonstrating reliable color imaging. Therefore, this study successfully demonstrates filter-free color-imaging by integrating high-performance patterned and multicomponent perovskite photodetectors, highlighting the potential of such detectors for advanced optoelectronic applications, including hyperspectral imaging.

High-bandwidth light inputting multilevel photoelectric memory based on thin-film transistor with a floating gate of CsPbBr3/CsPbI3 blend quantum dots.

The electronic-photonic convergent systems can overcome the data transmission bottleneck for microchips by enabling processor and memory chips with high-bandwidth optical input/output. However, current silicon-based electronic-photonic systems require various functional devices/components to convert high-bandwidth optical signals into electrical ones, thus making further integrations of sophisticated systems rather difficult. Here, we demonstrate thin-film transistor-based photoelectric memories employing CsPbBr3/CsPbI3 blend perovskite quantum dots (PQDs) as a floating gate, and multilevel memory cells are achieved under programming and erasing modes, respectively, by imputing high-bandwidth optical signals. For different bandwidth light input (i.e. 500-550, 575-650 and 675-750 nm) with the same intensity, three levels of programming window (i.e. 3.7, 1.9 and 0.8 V) and erasing window (i.e. -1.9, -0.6 and -0.1 V) are obtained under electrical pulses, respectively. This is because the blend PQDs have two different bandgaps, and different amounts of photo-generated carriers can be produced for different wavelength optical inputs. It is noticed that the 675-750 nm light inputs have no effects on both programming and erasing windows because of no photo-carriers generation. Four memory states are demonstrated, showing enough large gaps (1.12-5.61 V) between each other, good data retention and programming/erasing endurance. By inputting different optical signals, different memory states can be switched easily. Therefore, this work directly demonstrates high-bandwidth light inputting multilevel memory cells for novel electronic-photonic systems.

Three-Dimensional Nanoscale Flexible Memristor Networks with Ultralow Power for Information Transmission and Processing Application.

To construct an artificial intelligence system with high efficient information integration and computing capability like the human brain, it is necessary to realize the biological neurotransmission and information processing in artificial neural network (ANN), rather than a single electronic synapse as most reports. Because the power consumption of single synaptic event is ∼10 fJ in biology, designing an intelligent memristors-based 3D ANN with energy consumption lower than femtojoule-level (e.g., attojoule-level) and faster operating speed than millisecond-level makes it possible for constructing a higher energy efficient and higher speed computing system than the human brain. In this paper, a flexible 3D crossbar memristor array is presented, exhibiting the multilevel information transmission functionality with the power consumption of 4.28 aJ and the response speed of 50 ns per synaptic event. This work is a significant step toward the development of an ultrahigh efficient and ultrahigh-speed wearable 3D neuromorphic computing system.

Charge-Trap Memory Based on Hybrid 0D Quantum Dot-2D WSe2 Structure.

Recently, layered ultrathin 2D semiconductors, such as MoS2 and WSe2 are widely studied in nonvolatile memories because of their excellent electronic properties. Additionally, discrete 0D metallic nanocrystals and quantum dots (QDs) are considered to be outstanding charge-trap materials. Here, a charge-trap memory device based on a hybrid 0D CdSe QD-2D WSe2 structure is demonstrated. Specifically, ultrathin WSe2 is employed as the channel of the memory, and the QDs serve as the charge-trap layer. This device shows a large memory window exceeding 18 V, a high erase/program current ratio (reaching up to 104 ), four-level data storage ability, stable retention property, and high endurance of more than 400 cycles. Moreover, comparative experiments are carried out to prove that the charges are trapped by the QDs embedded in the Al2 O3 . The combination of 2D semiconductors with 0D QDs opens up a novelty field of charge-trap memory devices.

2D negative capacitance field-effect transistor with organic ferroelectrics.

In the past fifty years, complementary metal-oxide-semiconductor integrated circuits have undergone significant development, but Moore's law will soon come to an end. In order to break through the physical limit of Moore's law, 2D materials have been widely used in many electronic devices because of their high mobility and excellent mechanical flexibility. And the emergence of a negative capacitance field-effect transistor (NCFET) could not only break the thermal limit of conventional devices, but reduce the operating voltage and power consumption. This paper demonstrates a 2D NCFET that treats molybdenum disulfide as a channel material and organic P(VDF-TrFE) as a gate dielectric directly. This represents a new attempt to prepare NCFETs and produce flexible electronic devices. It exhibits a 10^6 on-/off-current ratio. And the minimum subthreshold swing (SS) of the 21 mV/decade and average SS of the 44 mV/decade in four orders of magnitude of drain current can also be observed at room temperature of 300 K.

Eliminating Overerase Behavior by Designing Energy Band in High-Speed Charge-Trap Memory Based on WSe2.

Atomic crystal charge trap memory, as a new concept of nonvolatile memory, possesses an atomic level flatness interface, which makes them promising candidates for replacing conventional FLASH memory in the future. Here, a 2D material WSe2 and a 3D Al2 O3 /HfO2 /Al2 O3 charge-trap stack are combined to form a charge-trap memory device with a separation of control gate and memory stack. In this device, the charges are erased/written by built-in electric field, which significantly enhances the write speed to 1 µs. More importantly, owing to the elaborate design of the energy band structure, the memory only captures electrons with a large electron memory window over 20 V and trap selectivity about 13, both of them are the state-of-the-art values ever reported in FLASH memory based on 2D materials. Therefore, it is demonstrated that high-performance charge trap memory based on WSe2 without the fatal overerase issue in conventional FLASH memory can be realized to practical application.

Tunable SnSe2 /WSe2 Heterostructure Tunneling Field Effect Transistor.

The burgeoning 2D semiconductors can maintain excellent device electrostatics with an ultranarrow channel length and can realize tunneling by electrostatic gating to avoid deprivation of band-edge sharpness resulting from chemical doping, which make them perfect candidates for tunneling field effect transistors. Here this study presents SnSe2 /WSe2 van der Waals heterostructures with SnSe2 as the p-layer and WSe2 as the n-layer. The energy band alignment changes from a staggered gap band offset (type-II) to a broken gap (type-III) when changing the negative back-gate voltage to positive, resulting in the device operating as a rectifier diode (rectification ratio ~104 ) or an n-type tunneling field effect transistor, respectively. A steep average subthreshold swing of 80 mV dec-1 for exceeding two decades of drain current with a minimum of 37 mV dec-1 at room temperature is observed, and an evident trend toward negative differential resistance is also accomplished for the tunneling field effect transistor due to the high gate efficiency of 0.36 for single gate devices. The ION /IOFF ratio of the transfer characteristics is >106 , accompanying a high ON current >10-5 A. This work presents original phenomena of multilayer 2D van der Waals heterostructures which can be applied to low-power consumption devices.

Various and Tunable Transport Properties of WSe2 Transistor Formed by Metal Contacts.

The abundant electronic and optical properties of 2D materials that are just one-atom thick pave the way for many novel electronic applications. One important application is to explore the band-to-band tunneling in the heterojunction built by different 2D materials. Here, a gate-controlled WSe2 transistor is constructed by using different work function metals to form the drain (Pt) and source (Cr) electrodes. The device can be gate-modulated to exhibit three modes of operation, i.e., the tunneling mode with remarkable negative differential resistance, the transition mode with a second electron tunneling phenomenon for backward bias, and finally the conventional diode mode with rectifying characteristics. In contrast to the heterojunctions built by different 2D materials, these devices show significantly enhanced tunneling current by two orders of magnitude, which may largely benefit from the clean interfaces. These results pave the way toward design of novel electronic devices using the modulation of metal work functions.

WSe2/MoS2 and MoTe2/SnSe2 van der Waals heterostructure transistors with different band alignment.

Heterostructure field-effect transistors (hetero-FETs) are experimentally demonstrated, consisting of van der Waals heterostructure channels based on a 2D semiconductor. By optimally selecting the band alignment of the heterostructure channels, different output characteristics of the hetero-FETs were achieved. In atomically thin WSe2/MoS2 hetero-FET with staggered energy band, the oscillating transfer characteristic and negative transconductance were realized. With near-broken-gap alignment in the MoTe2/SnSe2 heterostructure channel, a superior reverse-biased current was obtained in the hetero-FETs, which can be analyzed as typical tunneling current. Our study on the hetero-FET-based atomically thin van der Waals heterostructure channel, provides significant inspiration and reference to novel heterostructure FETs.

Surface-plasmon mediated photoluminescence enhancement of Pt-coated ZnO nanowires by inserting an atomic-layer-deposited Al2O3 spacer layer.

Surface-plasmon mediated photoluminescence emission enhancement has been investigated for ZnO nanowire (NW)/Pt nanoparticle (NP) nanostructures by inserting an Al2O3 spacer layer. The thickness of the Al2O3 spacer layer and of the Pt NPs capped on the ZnO NWs are well controlled by atomic layer deposition. It is found that the photoluminescence property of the ZnO NW/Al2O3/Pt hybrid structure is highly tunable with respect to the thickness of the inserted Al2O3 spacer layer. The highest enhancement (∼14 times) of the near band emission of ZnO NWs is obtained with an optimized Al2O3 spacer layer thickness of 10 nm leading to a ultraviolet-visible emission ratio of 271.2 compared to 18.8 for bare ZnO NWs. The enhancement of emission is influenced by a Förster-type non-radiative energy transfer process of the exciton energy from ZnO NWs to Pt NPs as well as the coupling effect between excitons of ZnO NWs and surface plasmons of Pt NPs. The highly versatile and tunable photoluminescence properties of Pt-coated ZnO NWs achieved by introducing an Al2O3 spacer layer demonstrate their potential application in highly efficient optoelectronic devices.

Photoluminescence enhancement of ZnO nanowire arrays by atomic layer deposition of ZrO2 layers and thermal annealing.

The effects of shell thickness and rapid thermal annealing on photoluminescence properties of one-dimensional ZnO/ZrO2 core/shell nanowires (NWs) are studied in this work. The ZnO/ZrO2 core/shell structures were synthesized by coating thin ZrO2 layers on the surface of ZnO NWs using atomic layer deposition. The morphological and structural characterization studies reveal that the ZrO2 shells have a polycrystalline structure, which are uniformly and conformally coated on the high quality single-crystal ZnO NWs. As compared with bare ZnO NWs, the ZnO/ZrO2 core/shell structures show a remarkable and continuous enhancement of ultraviolet (UV) emission in intensity with increasing ZrO2 shell thickness up to 10 nm. The great improvement mechanism of the UV emission arises from the surface passivation and the efficient carrier confinement effect of the type-I core/shell system. Moreover, it is observed that the UV emission of ZnO/ZrO2 core/shell structures after thermal annealing increases with increasing annealing temperature. The dominant surface exciton (SX) emission in the bare ZnO NWs and the ZnO/ZrO2 core/shell nanostructures has been detected in the low temperature photoluminescence spectra. A blue shift of the NBE emission peak as well as the varied decay rate of the SX emission intensity are also found in the ZnO NWs after the growth of ZrO2 shells and further thermal treatment. Our results suggest that the ZnO/ZrO2 core/shell nanostructures could be widely implemented in the optical and electronic devices in the future.

Effects of ZnO seed layer annealing temperature on the properties of n-ZnO NWs/Al(2)O(3)/p-Si heterojunction.

Effects of ZnO seed layer annealing temperature on the characteristics of the n-ZnO nanowires/Al(2)O(3)/p-Si heterojunction are investigated. Well-aligned ZnO nanowires (NWs) are grown through a simple hydrothermal method. Both the insertion of Al(2)O(3) buffer layer and the annealing treatment of ZnO seed layer are advantageous for the growth of ZnO NWs. This leads to a relatively high rectification ratio of up to 7.8 × 10(3) at ± 4.0 V in ZnO NWs/Al(2)O(3)/p-Si heterojunction photodetectors. The photoelectrical property of n-ZnO/p-Si photodetectors with an enhanced UV/dark current ratio as high as 30 under a reverse bias of 4.0 V is obtained.

Improved photoelectrical properties of n-ZnO/p-Si heterojunction by inserting an optimized thin Al2O3 buffer layer.

The n-ZnO/p-Si heterojunction with an ultrathin Al2O3 buffer layer was prepared by atomic layer deposition. X-ray diffraction revealed that the crystalline quality of (100)-oriented ZnO films was improved with an Al2O3 buffer layer. The n-ZnO/p-Si heterojunction with 5 nm inserted Al2O3 layer shows the best electrical characteristics, with a dark current of 0.5 µA at a reverse bias of -2 V and increasing the photo-to-dark current ratio effectively by 8 times. These results demonstrated that Al2O3 buffer layer with optimized thickness exhibits significant advantages in enhancing the crystal quality of ZnO film and improving the photoelectrical properties of n-ZnO/p-Si photodetectors.

Enhancement of Electrical Safe Operation Area of 60 V nLDMOS by Engineering of Reduced Surface Electrical Field in the Drift Region.

To enhance the electrical safe operation area (eSOA) of laterally diffused metal oxide semiconductor (LDMOS) transistors, a novel reduced surface electric field (Resurf) structure in the n-drift region is proposed, which was fabricated by ion implantation at the surface of the LDMOS drift region and by drift region dimension optimization. Technology computer-aided design (TCAD) simulations show that the optimal value of Resurf ion implantation dose 1 × 1012 cm-2 can reduce the surface electric field in the n-drift region effectively, thereby improving the ON-state breakdown voltage of the device (BVon). In addition, the extended n-drift region length of the Ld design also improves device BVon significantly, and is aimed at reducing the current density and the electric field, and eventually suppressing the n-drift region impact ionization. The results show that the novel 60 V nLDMOS has a competitive BVon performance of 106.9 V, which is about 20% higher than that of the conventional one. Meanwhile, the OFF-state breakdown voltage of the device (BVoff) of 88.4 V and the specific ON-resistance (RON,sp) of 129.7 mΩ⋅mm2 exhibit only a slight sacrifice.

Graded-Band-Gap Zinc-Tin Oxide Thin-Film Transistors with a Vertically Stacked Structure for Wavelength-Selective Photodetection.

Filter-free wavelength-selective photodetectors have garnered significant attention due to the growing demand for smart sensors, artificial intelligence, the Internet of Everything, and so forth. However, the challenges associated with large-scale preparation and compatibility with complementary metal-oxide-semiconductor (CMOS) technology limit their wide-ranging applications. In this work, we address the challenges by constructing vertically stacked graded-band-gap zinc-tin oxide (ZTO) thin-film transistors (TFTs) specifically designed for wavelength-selective photodetection. The ZTO thin films with various band gaps are fabricated via atomic layer deposition (ALD) by varying the ALD cycle ratios of zinc oxide (ZnO) and SnO2. The ZTO film with a small Sn ratio exhibits a decreased band gap, and the resultant TFT shows a degraded performance, which can be attributed to the Sn4+ dopant introducing a series of deep-state energy levels in the ZnO band gap. As the ratio of Sn increases further, the band gap of the ZTO also increases, and the mobility of the ZTO TFT increases up to 30 cm2/V s, with a positive shift of the threshold voltage. The photodetectors employing ZTO thin films with distinct band gaps show different spectral responsivities. Then, vertically stacked ZTO (S-ZTO) thin films, with gradient band gaps increasing from the bottom to the top, have been successfully deposited using consecutive ALD technology. The S-ZTO TFT shows decent performance with a mobility of 18.4 cm2/V s, a threshold voltage of 0.5 V, an on-off current ratio higher than 107, and excellent stability under ambient conditions. The resultant S-ZTO TFT also exhibits obviously distinct photoresponses to light at different wavelength ranges. Furthermore, a device array of S-ZTO TFTs demonstrates color imaging by precisely reconstructing patterned illuminations with different wavelengths. Therefore, this work provides CMOS-compatible and structure-compact wavelength-selective photodetectors for advanced and integrable optoelectronic applications.