Solution-Processed Carbon Nanotube True Random Number Generator.

With the growing adoption of interconnected electronic devices in consumer and industrial applications, there is an increasing demand for robust security protocols when transmitting and receiving sensitive data. Toward this end, hardware true random number generators (TRNGs), commonly used to create encryption keys, offer significant advantages over software pseudorandom number generators. However, the vast network of devices and sensors envisioned for the "Internet of Things" will require small, low-cost, and mechanically flexible TRNGs with low computational complexity. These rigorous constraints position solution-processed semiconducting single-walled carbon nanotubes (SWCNTs) as leading candidates for next-generation security devices. Here, we demonstrate the first TRNG using static random access memory (SRAM) cells based on solution-processed SWCNTs that digitize thermal noise to generate random bits. This bit generation strategy can be readily implemented in hardware with minimal transistor and computational overhead, resulting in an output stream that passes standardized statistical tests for randomness. By using solution-processed semiconducting SWCNTs in a low-power, complementary architecture to achieve TRNG, we demonstrate a promising approach for improving the security of printable and flexible electronics.

Large-area, low-voltage, antiambipolar heterojunctions from solution-processed semiconductors.

The emergence of semiconducting materials with inert or dangling bond-free surfaces has created opportunities to form van der Waals heterostructures without the constraints of traditional epitaxial growth. For example, layered two-dimensional (2D) semiconductors have been incorporated into heterostructure devices with gate-tunable electronic and optical functionalities. However, 2D materials present processing challenges that have prevented these heterostructures from being produced with sufficient scalability and/or homogeneity to enable their incorporation into large-area integrated circuits. Here, we extend the concept of van der Waals heterojunctions to semiconducting p-type single-walled carbon nanotube (s-SWCNT) and n-type amorphous indium gallium zinc oxide (a-IGZO) thin films that can be solution-processed or sputtered with high spatial uniformity at the wafer scale. The resulting large-area, low-voltage p-n heterojunctions exhibit antiambipolar transfer characteristics with high on/off ratios that are well-suited for electronic, optoelectronic, and telecommunication technologies.

Aerosol jet printed, low voltage, electrolyte gated carbon nanotube ring oscillators with sub-5 µs stage delays.

A central challenge for printed electronics is to achieve high operating frequencies (short transistor switching times) at low supply biases compatible with thin film batteries. In this report, we demonstrate partially printed five-stage ring oscillators with >20 kHz operating frequencies and stage delays <5 µs at supply voltages below 3 V. The fastest ring oscillator achieved 1.2 µs delay time at 2 V supply. The inverter stages in these ring oscillators were based on ambipolar thin film transistors (TFTs) employing semiconducting, single-walled carbon nanotube (CNT) networks and a high capacitance (∼1 µF/cm(2)) ion gel electrolyte as the gate dielectric. All materials except the source and drain electrodes were aerosol jet printed. The TFTs exhibited high electron and hole mobilities (∼20 cm(2)/(V s)) and ON/OFF current ratios (up to 10(5)). Inverter switching times t were systematically characterized as a function of transistor channel length and ionic conductivity of the gel dielectric, demonstrating that both the semiconductor and the ion gel play a role in switching speed. Quantitative scaling analysis suggests that with suitable optimization low voltage, printed ion gel gated CNT inverters could operate at frequencies on the order of 1 MHz.

Subnanowatt carbon nanotube complementary logic enabled by threshold voltage control.

In this Letter, we demonstrate thin-film single-walled carbon nanotube (SWCNT) complementary metal-oxide-semiconductor (CMOS) logic devices with subnanowatt static power consumption and full rail-to-rail voltage transfer characteristics as is required for logic gate cascading. These results are enabled by a local metal gate structure that achieves enhancement-mode p-type and n-type SWCNT thin-film transistors (TFTs) with widely separated and symmetric threshold voltages. These complementary SWCNT TFTs are integrated to demonstrate CMOS inverter, NAND, and NOR logic gates at supply voltages as low as 0.8 V with ideal rail-to-rail operation, subnanowatt static power consumption, high gain, and excellent noise immunity. This work provides a direct pathway for solution processable, large area, power efficient SWCNT advanced logic circuits and systems.

3SAT on an all-to-all-connected CMOS Ising solver chip.

This work solves 3SAT, a classical NP-complete problem, on a CMOS-based Ising hardware chip with all-to-all connectivity. The paper addresses practical issues in going from algorithms to hardware. It considers several degrees of freedom in mapping the 3SAT problem to the chip-using multiple Ising formulations for 3SAT; exploring multiple strategies for decomposing large problems into subproblems that can be accommodated on the Ising chip; and executing a sequence of these subproblems on CMOS hardware to obtain the solution to the larger problem. These are evaluated within a software framework, and the results are used to identify the most promising formulations and decomposition techniques. These best approaches are then mapped to the all-to-all hardware, and the performance of 3SAT is evaluated on the chip. Experimental data shows that the deployed decomposition and mapping strategies impact SAT solution quality: without our methods, the CMOS hardware cannot achieve 3SAT solutions on SATLIB benchmarks. Under the assumption of some hardware improvements, our chip-based 3SAT solver demonstrates a remarkable 250 × acceleration compared to Tabu search in dwave-hybrid on a CPU.

BioTranslator: Inferring R-Peaks from Ambulatory Wrist-Worn PPG Signal.

Advancements in wireless sensor networks (WSN) technology and miniaturization of wearable sensors have enabled long-term continuous pervasive biomedical signal monitoring. Wrist-worn photoplethysmography (PPG) sensors have gained popularity given their form factor. However the signal quality suffers due to motion artifacts when used in ambulatory settings, making vital parameter estimation a challenging task. In this paper, we present a novel deep learning framework, BioTranslator, for computing the instantaneous heart rate (IHR), using wrist-worn PPG signals collected during physical activity. Using one-dimensional Convolution-Deconvolution Network, we translate a single channel PPG signal to an electrocardiogram(ECG)-like time series signal, from which relevant R-peak information can be inferred enabling IHR measures. The proposed network configuration was evaluated on 12 subjects of the TROIKA dataset, involved in physical activity. The proposed network identifies 92.8% of R-peaks, besides achieving a mean absolute error of 51±6.3ms with respect to reference ECG-derived IHR.

CorNET: Deep Learning Framework for PPG-Based Heart Rate Estimation and Biometric Identification in Ambulant Environment.

Advancements in wireless sensor network technologies have enabled the proliferation of miniaturized body-worn sensors, capable of long-term pervasive biomedical signal monitoring. Remote cardiovascular monitoring has been one of the beneficiaries of this development, resulting in non-invasive, photoplethysmography (PPG) sensors being used in ambulatory settings. Wrist-worn PPG, although a popular alternative to electrocardiogram, suffers from motion artifacts inherent in daily life. Hence, in this paper, we present a novel deep learning framework (CorNET) to efficiently estimate heart rate (HR) information and perform biometric identification (BId) using only a wrist-worn, single-channel PPG signal collected in ambulant environment. We have formulated a completely personalized data-driven approach, using a four-layer deep neural network. Two convolution neural network layers are used in conjunction with two long short-term memory layers, followed by a dense output layer for modeling the temporal sequence inherent within the pulsatile signal representative of cardiac activity. The final dense layer is customized with respect to the application, functioning as: regression layer-having a single neuron to predict HR; classification layer-two neurons that identify a subject among a group. The proposed network was evaluated on the TROIKA dataset having 22 PPG records collected during various physical activities. We achieve a mean absolute error of 1.47 ± 3.37 beats per minute for HR estimation and an average accuracy of 96% for BId on 20 subjects. CorNET was further evaluated successfully in an ambulant use-case scenario with custom sensors for two subjects.

Dynamic Memory Cells Using MoS2 Field-Effect Transistors Demonstrating Femtoampere Leakage Currents.

Two-dimensional semiconductors such as transition-metal dichalcogenides (TMDs) are of tremendous interest for scaled logic and memory applications. One of the most promising TMDs for scaled transistors is molybdenum disulfide (MoS2), and several recent reports have shown excellent performance and scalability for MoS2 MOSFETs. An often overlooked feature of MoS2 is that its wide band gap (1.8 eV in monolayer) and high effective masses should lead to extremely low off-state leakage currents. These features could be extremely important for dynamic memory applications where the refresh rate is the primary factor affecting the power consumption. Theoretical predictions suggest that leakage currents in the 10(-18) to 10(-15) A/µm range could be possible, even in scaled transistor geometries. Here, we demonstrate the operation of one- and two-transistor dynamic memory circuits using MoS2 MOSFETs. We characterize the retention times in these circuits and show that the two-transistor memory cell reveals MoS2 MOSFETs leakage currents as low as 1.7 × 10(-15) A/µm, a value that is below the noise floor of conventional DC measurements. These results have important implications for the future use of MoS2 MOSFETs in low-power circuit applications.

Solution-processed carbon nanotube thin-film complementary static random access memory.

Over the past two decades, extensive research on single-walled carbon nanotubes (SWCNTs) has elucidated their many extraordinary properties, making them one of the most promising candidates for solution-processable, high-performance integrated circuits. In particular, advances in the enrichment of high-purity semiconducting SWCNTs have enabled recent circuit demonstrations including synchronous digital logic, flexible electronics and high-frequency applications. However, due to the stringent requirements of the transistors used in complementary metal-oxide-semiconductor (CMOS) logic as well as the absence of sufficiently stable and spatially homogeneous SWCNT thin-film transistors, the development of large-scale SWCNT CMOS integrated circuits has been limited in both complexity and functionality. Here, we demonstrate the stable and uniform electronic performance of complementary p-type and n-type SWCNT thin-film transistors by controlling adsorbed atmospheric dopants and incorporating robust encapsulation layers. Based on these complementary SWCNT thin-film transistors, we simulate, design and fabricate arrays of low-power static random access memory circuits, achieving large-scale integration for the first time based on solution-processed semiconductors.

Aerosol jet printed, sub-2 V complementary circuits constructed from P- and N-type electrolyte gated transistors.

Printed low-voltage complementary inverters based on electrolyte gated transistors are demonstrated. The printed complementary inverters showed gain of 18 and power dissipation below 10 nW. 5-stage ring oscillators operate at 2 V with an oscillation frequency of 2.2 kHz, corresponding to stage delays of less than 50 µs. The printed circuits exhibit good stability under continuous dynamic operation.

Aerosol-jet-printed, 1 volt H-bridge drive circuit on plastic with integrated electrochromic pixel.

In this report, we demonstrate a printed, flexible, and low-voltage circuit that successfully drives a polymer electrochromic (EC) pixel as large as 4 mm(2) that is printed on the same substrate. All of the key components of the drive circuitry, namely, resistors, capacitors, and transistors, were aerosol-jet-printed onto a plastic foil; metallic electrodes and interconnects were the only components prepatterned on the plastic by conventional photolithography. The large milliampere drive currents necessary to switch a 4 mm(2) EC pixel were controlled by printed electrolyte-gated transistors (EGTs) that incorporate printable ion gels for the gate insulator layers and poly(3-hexylthiophene) for the semiconductor channels. Upon application of a 1 V input pulse, the circuit switches the printed EC pixel ON (red) and OFF (blue) two times in approximately 4 s. The performance of the circuit and the behavior of the individual resistors, capacitors, EGTs, and the EC pixel are analyzed as functions of the printing parameters and operating conditions.

Printed, sub-3V digital circuits on plastic from aqueous carbon nanotube inks.

Printing electronic components on plastic foils with functional liquid inks is an attractive approach for achieving flexible and low-cost circuitry for applications such as bendable displays and large-area sensors. The challenges for printed electronics, however, include characteristically slow switching frequencies and associated high supply voltages, which together impede widespread application. Combining printable high-capacitance dielectrics with printable high-mobility semiconductors could potentially solve these problems. Here we demonstrate fast, flexible digital circuits based on semiconducting carbon nanotube (CNT) networks and high-capacitance ion gel gate dielectrics, which were patterned by jet printing of liquid inks. Ion gel-gated CNT thin-film transistors (TFTs) with 50 microm channel lengths display ambipolar transport with electron and hole mobilities >20 cm(2)/V.s; these devices form the basis of printed inverters, NAND gates, and ring oscillators on both polyimide and SiO(2) substrates. Five-stage ring oscillators achieve frequencies >2 kHz at supply voltages of 2.5 V, corresponding to stage delay times of 50 micros. This performance represents a substantial improvement for printed circuitry fabricated from functional liquid inks.