Vacuum levitation and motion control on chip.

By isolating from the environment and precisely controlling mesoscopic objects, levitation in vacuum has evolved into a versatile technique that has already benefited diverse scientific directions, from force sensing and thermodynamics to materials science and chemistry. It also holds great promise for advancing the study of quantum mechanics in the unexplored macroscopic regime. However, most current levitation platforms are complex and bulky. Recent efforts in miniaturization of vacuum levitation set-ups have comprised electrostatic and optical traps, but robustness is still a concern for integration into confined settings, such as cryostats or portable devices. Here we show levitation and motion control in high vacuum of a silica nanoparticle at the surface of a hybrid optical-electrostatic chip. By combining fibre-based optical trapping and sensitive position detection with cold damping through planar electrodes, we cool the particle motion to a few hundred phonons. We envisage that our fully integrated platform is the starting point for on-chip devices combining integrated photonics and nanophotonics with precisely engineered electric potentials, enhancing control over the particle motion towards complex state preparation and read-out.

The Michelangelo step: removing scalloping and tapering effects in high aspect ratio through silicon vias.

We present here, for the first time, a fabrication technique that allows manufacturing scallop free,non-tapered, high aspect ratio in through-silicon vias (TSVs) on silicon wafers. TSVs are among major technology players in modern high-volume manufacturing as they enable 3D chip integration. However, the usual standardized TSV fabrication process has to deal with scalloping, an imperfection in the sidewalls caused by the deep reactive ion etching. The presence of scalloping causes stress and field concentration in the dielectric barrier, thereby dramatically impacting the following TSV filling step, which is performed by means of electrochemical plating. So, we propose here a new scallop free and non-tapered approach to overcome this challenge by adding a new step to the standard TSV procedure exploiting the crystalline orientation of silicon wafers. Thank to this new step, that we called "Michelangelo", we obtained an extremely well polishing of the TSV holes, by reaching atomic-level smoothness and a record aspect ratio of 28:1. The Michelangelo step will thus drastically reduce the footprint of 3D structures and will allow unprecedented efficiency in 3D chip integration.