Operating region-dependent characteristics of weight updates in synaptic In-Ga-Zn-O thin-film transistors.

We present a study on characteristics of operating region-dependent weight updates in a synaptic thin-film transistor (Syn-TFT) with an amorphous In-Ga-Zn-O (IGZO) channel layer. For a synaptic behavior (e.g. a memory phenomenon) of the IGZO TFT, a defective oxide (e.g. SiO2) is intentionally used for a charge trapping due to programming pulses to the gate terminal. Based on this synaptic behavior, a conductance of the Syn-TFT is modulated depending on the programming pulses, thus weight updates. This weight update characteristics of the Syn-TFT is analyzed in terms of a dynamic ratio (drw) for two operating regions (i.e. the above-threshold and sub-threshold regimes). Here, the operating region is chosen depending on the level of the gate read-voltage relative to the threshold voltage of the Syn-TFT. To verify these, the static and pulsed characteristics of the fabricated Syn-TFT are monitored experimentally. As experimental results, it is found that the drw of the sub-threshold regime is larger compared to the above-threshold regime. In addition, the weight linearity in the sub-threshold regime is observed to be better compared to the above-threshold regime. Since it is expected that either the drw or weight linearity can affect performances (e.g. a classification accuracy) of an analog accelerator (AA) constructed with the Syn-TFTs, the AA simulation is performed to check this with a crossbar simulator.

Synaptic Weight Evolution and Charge Trapping Mechanisms in a Synaptic Pass-Transistor Operation With a Direct Potential Output.

We present an intensive study on the weight modulation and charge trapping mechanisms of the synaptic transistor based on a pass-transistor concept for the direct voltage output. In this article, the pass-transistor concept for a metal-oxide-semiconductor field-effect transistor is employed to a synaptic transistor with a charge trapping layer, which is named a synaptic pass transistor (SPT). Based on this SPT concept, the voltage signal would be provided at the output terminal directly without requiring a complicated circuitry, whereas the conventional synaptic transistor with the current output needs a conversion circuit. For the SPT, the definition of the synaptic weight as a transfer efficiency and operation principles of the SPT with charge-trapping mechanisms is analyzed theoretically. The respective semiconductor device simulation results, such as synaptic output and weight modulations as a function of time for a synaptic depression and facilitation, are presented with detailed analysis. Also, it is shown that an SPT array configuration can perform a synaptic scaling by itself, i.e., a self-normalization of the weight, which is confirmed with the simulation results of learning a simple classification example. Moreover, to verify the potential usage of the SPT array as an analog artificial intelligence accelerator, a classification task for a standard data set, e.g., Modified National Institute of Standards and Technology database (MNIST), is also tested by monitoring the accuracy. Finally, it is found that SPTs proposed here can exhibit low power consumption at a device level as well as sufficient accuracy at the array level while more closely mimicking the biological synapse.