Device quantization policy in variation-aware in-memory computing design.

Device quantization of in-memory computing (IMC) that considers the non-negligible variation and finite dynamic range of practical memory technology is investigated, aiming for quantitatively co-optimizing system performance on accuracy, power, and area. Architecture- and algorithm-level solutions are taken into consideration. Weight-separate mapping, VGG-like algorithm, multiple cells per weight, and fine-tuning of the classifier layer are effective for suppressing inference accuracy loss due to variation and allow for the lowest possible weight precision to improve area and energy efficiency. Higher priority should be given to developing low-conductance and low-variability memory devices that are essential for energy and area-efficiency IMC whereas low bit precision (< 3b) and memory window (< 10) are less concerned.

Determining motions with an IMU during level walking and slope and stair walking.

This study investigated whether using an inertial measurement unit (IMU) can identify different walking conditions, including level walking (LW), descent (DC) and ascent (AC) slope walking as well as downstairs (DS) and upstairs (US) walking. Thirty healthy participants performed walking under five conditions. The IMU was stabilised on the exterior of the left shoe. The data from IMU were used to establish a customised prediction model by cut point and a prediction model by using deep learning method. The accuracy of both prediction models was evaluated. The customised prediction model combining the angular velocity of dorsi-plantar flexion in the heel-strike (HS) and toe-off (TO) phases can distinctly determine real conditions during DC and AC slope, DS, and LW (accuracy: 86.7-96.7%) except for US walking (accuracy: 60.0%). The prediction model established by deep learning using the data of three-axis acceleration and three-axis gyroscopes can also distinctly identify DS, US, and LW with 90.2-90.7% accuracy and 84.8% and 82.4% accuracy for DC and AC slope walking, respectively. In conclusion, inertial measurement units can be used to identify walking patterns under different conditions such as slopes and stairs with customised prediction model and deep learning prediction model.

Fast SIFT design for real-time visual feature extraction.

Visual feature extraction with scale invariant feature transform (SIFT) is widely used for object recognition. However, its real-time implementation suffers from long latency, heavy computation, and high memory storage because of its frame level computation with iterated Gaussian blur operations. Thus, this paper proposes a layer parallel SIFT (LPSIFT) with integral image, and its parallel hardware design with an on-the-fly feature extraction flow for real-time application needs. Compared with the original SIFT algorithm, the proposed approach reduces the computational amount by 90% and memory usage by 95%. The final implementation uses 580-K gate count with 90-nm CMOS technology, and offers 6000 feature points/frame for VGA images at 30 frames/s and ∼ 2000 feature points/frame for 1920 × 1080 images at 30 frames/s at the clock rate of 100 MHz.

A 124 Mpixels/s VLSI design for histogram-based joint bilateral filtering.

This paper presents an efficient and scalable design for histogram-based bilateral filtering (BF) and joint BF (JBF) by memory reduction methods and architecture design techniques to solve the problems of high memory cost, high computational complexity, high bandwidth, and large range table. The presented memory reduction methods exploit the progressive computing characteristics to reduce the memory cost to 0.003%-0.020%, as compared with the original approach. Furthermore, the architecture design techniques adopt range domain parallelism and take advantage of the computing order and the numerical properties to solve the complexity, bandwidth, and range-table problems. The example design with a 90-nm complementary metal-oxide-semiconductor process can deliver the throughput to 124 Mpixels/s with 356-K gate counts and 23-KB on-chip memory.