Low-power wireless ECG acquisition and classification system for body sensor networks.

A low-power biosignal acquisition and classification system for body sensor networks is proposed. The proposed system consists of three main parts: 1) a high-pass sigma delta modulator-based biosignal processor (BSP) for signal acquisition and digitization, 2) a low-power, super-regenerative on-off keying transceiver for short-range wireless transmission, and 3) a digital signal processor (DSP) for electrocardiogram (ECG) classification. The BSP and transmitter circuits, which are the body-end circuits, can be operated for over 80 days using two 605 mAH zinc-air batteries as the power supply; the power consumption is 586.5 µW. As for the radio frequency receiver and DSP, which are the receiving-end circuits that can be integrated in smartphones or personal computers, power consumption is less than 1 mW. With a wavelet transform-based digital signal processing circuit and a diagnosis control by cardiologists, the accuracy of beat detection and ECG classification are close to 99.44% and 97.25%, respectively. All chips are fabricated in TSMC 0.18-µm standard CMOS process.

A wireless ECG acquisition and classification system for body sensor networks.

This paper demonstrates a wireless ECG acquisition and classification system with a bio-signal processor (BSP), a super regenerative transceiver, and a digital signal processor (DSP). The BSP, which is implemented with low complexity architecture, includes only a low noise amplifier with chopping techniques and a high-pass sigma-delta modulator (HPSDM). The super-regenerative on-off keying (OOK) transceiver is applied for the low power, short range transmission and low date rate wireless communication. For the signal processing and analyzing, the DSP circuit is adopted in the receiver. The whole system is implemented in a TSMC 0.18 µm 1P6M CMOS process under the supply voltage of 1.2 V. In the near body node, the power consumption including a BSP and a transmitter is 587 µW only. With two PR44 zinc-air batteries of 605 mAh, the near body node circuit can be operated about 100 days. In the receiving node, the power consumption with a receiver and a DSP is 926 µW.

A low-power 13.56 MHz RF front-end circuit for implantable biomedical devices.

A low-power fully-integrated CMOS RF front-end circuit for a passive 13.56 MHz biomedical implant is presented. A 13.56 MHz binary phase shift keying (BPSK) signal is received by an internal coil. This front-end circuit is composed of a full-wave bridge rectifier, a linear regulator, a BPSK demodulator, and a clock/data recovery (CDR). A full-wave bridge rectifier converts the carrier waveform with the BPSK signal to an unregulated DC voltage. A linear regulator stabilizes the unregulated DC voltage to 1.8 V that serves as the DC source for the implant. A BPSK demodulator detects the incoming BPSK signal from the internal coil and translates the demodulated data to the CDR which can successfully recover the clock and data for the system controller. This chip with a core area of 0.45 mm(2) has been fabricated in a TSMC 0.18 µm 1P6M CMOS technology. The total power consumed is only 632 µW.

Low-power analog integrated circuits for wireless ECG acquisition systems.

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 µm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.