Cluster-type analogue memristor by engineering redox dynamics for high-performance neuromorphic computing.

Memristors, or memristive devices, have attracted tremendous interest in neuromorphic hardware implementation. However, the high electric-field dependence in conventional filamentary memristors results in either digital-like conductance updates or gradual switching only in a limited dynamic range. Here, we address the switching parameter, the reduction probability of Ag cations in the switching medium, and ultimately demonstrate a cluster-type analogue memristor. Ti nanoclusters are embedded into densified amorphous Si for the following reasons: low standard reduction potential, thermodynamic miscibility with Si, and alloy formation with Ag. These Ti clusters effectively induce the electrochemical reduction activity of Ag cations and allow linear potentiation/depression in tandem with a large conductance range (~244) and long data retention (~99% at 1 hour). Moreover, according to the reduction potentials of incorporated metals (Pt, Ta, W, and Ti), the extent of linearity improvement is selectively tuneable. Image processing simulation proves that the Ti4.8%:a-Si device can fully function with high accuracy as an ideal synaptic model.

Energy-Efficient III-V Tunnel FET-Based Synaptic Device with Enhanced Charge Trapping Ability Utilizing Both Hot Hole and Hot Electron Injections for Analog Neuromorphic Computing.

A charge trap device based on field-effect transistors (FET) is a promising candidate for artificial synapses because of its high reliability and mature fabrication technology. However, conventional MOSFET-based charge trap synapses require a strong stimulus for synaptic update because of their inefficient hot-carrier injection into the charge trapping layer, consequently causing a slow speed operation and large power consumption. Here, we propose a highly efficient charge trap synapse using III-V materials-based tunnel field-effect transistor (TFET). Our synaptic TFETs present superior subthreshold swing and improved charge trapping ability utilizing both carriers as charge trapping sources: hot holes created by impact ionization in the narrow bandgap InGaAs after being provided from the p+-source, and band-to-band tunneling hot electrons (BBHEs) generated at the abrupt p+n junctions in the TFETs. Thanks to these advances, our devices achieved outstanding efficiency in synaptic characteristics with a 5750 times faster synaptic update speed and 51 times lower sub-fJ/um2 energy consumption per single synaptic update in comparison to the MOSFET-based synapse. An artificial neural network (ANN) simulation also confirmed a high recognition accuracy of handwritten digits up to ∼90% in a multilayer perceptron neural network based on our synaptic devices.

Spiking Neural Network (SNN) With Memristor Synapses Having Non-linear Weight Update.

Among many artificial neural networks, the research on Spike Neural Network (SNN), which mimics the energy-efficient signal system in the brain, is drawing much attention. Memristor is a promising candidate as a synaptic component for hardware implementation of SNN, but several non-ideal device properties are making it challengeable. In this work, we conducted an SNN simulation by adding a device model with a non-linear weight update to test the impact on SNN performance. We found that SNN has a strong tolerance for the device non-linearity and the network can keep the accuracy high if a device meets one of the two conditions: 1. symmetric LTP and LTD curves and 2. positive non-linearity factors for both LTP and LTD. The reason was analyzed in terms of the balance between network parameters as well as the variability of weight. The results are considered to be a piece of useful prior information for the future implementation of emerging device-based neuromorphic hardware.