A Novel Channel Preparation Scheme to Optimize Program Disturbance in Three-Dimensional NAND Flash Memory.

The program disturbance characteristics of three-dimensional (3D) vertical NAND flash cell array architecture pose a critical reliability challenge due to the lower unselected word line (WL) pass bias (Vpass) window. In other words, the key contradiction of program disturbance is that the operational Vpass during the program's performance cannot be too high or too low. For instance, the 3D NAND program's operation string needs a lower Vpass bias to suppress unselected WL Vpass bias-induced Fowler-Nordheim tunneling (FN tunneling), but for the inhibited string, the unselected WL needs a higher Vpass bias to suppress selected WL program bias (Vpgm)-induced FN tunneling. In this paper, a systematical insight into the relationship between the channel potential and channel electron density is given. Based on this intensive investigation, we studied a novel channel preparation scheme using "Gate-induced drain leakage (GIDL) pre-charge". Our methodology does not require the introduction of any new structures in 3D NAND, or changes in the operational Vpass bias. Instead, the potential on the unselected channel is enhanced by exploiting the holes generated by the GIDL operation effectively, leading to significantly suppressed program disturbance and a larger pass disturb window. To validate the effectiveness of the "GIDL pre-charge" method, TCAD simulation and real silicon data are used.

Investigation of Erase Cycling Induced Joint Dummy Cell Disturbance in Dual-Deck 3D NAND Flash Memory.

To satisfy the increasing demands for more word-line (WL) layers, the dual-deck even triple-deck architecture has emerged in 3D NAND Flash. However, the new reliability issues that occurred at the joint region of two decks became a severe challenge for developing multiple-deck technology. This work reported an abnormal reliability issue introduced by erasing disturbance of the dummy WLs at the joint region (Joint-DMYs) under multiple cycling. More specifically, after several erase cycling stresses, the increasing joint-DMY's threshold voltage (Vt) due to the operational stress will finally result in additional disturbance to the adjacent data WLs. In this paper, we proposed this disturbance during erase originates from the backward injected electrons through FN tunneling based on our TCAD simulation result. Moreover, we also proposed an optimal erase scheme to reduce the backward electron injection and suppress the abnormal joint-DMY disturbance during the erase cycling.

Activation Enhancement and Grain Size Improvement for Poly-Si Channel Vertical Transistor by Laser Thermal Annealing in 3D NAND Flash.

The bit density is generally increased by stacking more layers in 3D NAND Flash. Lowering dopant activation of select transistors results from complex integrated processes. To improve channel dopant activation, the test structure of vertical channel transistors was used to investigate the influence of laser thermal annealing on dopant activation. The activation of channel doping by different thermal annealing methods was compared. The laser thermal annealing enhanced the channel activation rate by at least 23% more than limited temperature rapid thermal annealing. We then comprehensively explore the laser thermal annealing energy density on the influence of Poly-Si grain size and device performance. A clear correlation between grain size mean and grain size sigma, large grain size mean and sigma with large laser thermal annealing energy density. Large laser thermal annealing energy density leads to tightening threshold voltage and subthreshold swing distribution since Poly-Si grain size regrows for better grain size distribution with local grains optimization. As an enabler for next-generation technologies, laser thermal annealing will be highly applied in 3D NAND Flash for better device performance with stacking more layers, and opening new opportunities of novel 3D architectures in the semiconductor industry.

A Novel Capacitorless 1T DRAM with Embedded Oxide Layer.

A novel vertical dual surrounding gate transistor with embedded oxide layer is proposed for capacitorless single transistor DRAM (1T DRAM). The embedded oxide layer is innovatively used to improve the retention time by reducing the recombination rate of stored holes and sensing electrons. Based on TCAD simulations, the new structure is predicted to not only have the characteristics of fast access, random read and integration of 4F2 cell, but also to realize good retention and deep scaling. At the same time, the new structure has the potential of scaling compared with the conventional capacitorless 1T DRAM.

Dual-axis control of magnetic anisotropy in a single crystal Co2MnSi thin film through piezo-voltage-induced strain.

Voltage controlled magnetic anisotropy (VCMA) has been considered as an effective method in traditional magnetic devices with lower power consumption. In this article, we have investigated the dual-axis control of magnetic anisotropy in Co2MnSi/GaAs/PZT hybrid heterostructures through piezo-voltage-induced strain using longitudinal magneto-optical Kerr effect (LMOKE) microscopy. The major modification of in-plane magnetic anisotropy of the Co2MnSi thin film is controlled obviously by the piezo-voltages of the lead zirconate titanate (PZT) piezotransducer, accompanied by the coercivity field and magnetocrystalline anisotropy significantly manipulated. Because in-plane cubic magnetic anisotropy and uniaxial magnetic anisotropy coexist in the Co2MnSi thin film, the initial double easy axes of cubic split to an easiest axis (square loop) and an easier axis (two-step loop). While the stress direction is parallel to the [1-10] easiest axis (sample I), the square loop of the [1-10] direction could transform to a two-step loop under the negative piezo-voltages (compressed state). At the same time, the initial two-step loop of the [110] axis simultaneously changes to a square loop (the easiest axis). Otherwise, we designed and fabricated the sample II in which the PZT stress is parallel to the [110] two-step axis. The phenomenon of VCMA was also obtained along the [110] and [1-10] directions. However, the manipulated results of sample II were in contrast to those of the sample I under the piezo-voltages. Thus, an effective dual-axis regulation of the in-plane magnetization rotation was demonstrated in this work. Such a finding proposes a more optimized method for the magnetic logic gates and memories based on voltage-controlled magnetic anisotropy in the future.

The Optimization of Gate All Around-L-Shaped Bottom Select Transistor in 3D NAND Flash Memory.

In this work, the GAA (Gate All Around) L-Shaped bottom select transistor (BSG) in 3D NAND Flash Memory has been investigated. Different methods are proposed to optimize its performance from viewpoints of process and structure. BSG in 3D NAND is a novel device structure with two connected transistors: one is horizontal MOSFET (regarded as convention MOSFET) and one is vertical MOSFET (regarded as GAA transistor). With implant dose increasing in vertical channel, BSG Vth has much more tighter Vt distribution, which is beneficial for boosting potential improvement and program disturbance suppression. Meanwhile, BSG corner rounding is proposed to improve the characteristic of BSG. Experiment and TCAD simulation data are matches quite well, giving a way to improve cell characteristics distribution and self-boosting potential control in high density 3D NAND array.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors.

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Isolated nanographene crystals for nano-floating gate in charge trapping memory.

Graphene exhibits unique electronic properties, and its low dimensionality, structural robustness, and high work-function make it very promising as the charge storage media for memory applications. Along with the development of miniaturized and scaled up devices, nanostructured graphene emerges as an ideal material candidate. Here we proposed a novel non-volatile charge trapping memory utilizing isolate and uniformly distributed nanographene crystals as nano-floating gate with controllable capacity and excellent uniformity. Nanographene charge trapping memory shows large memory window (4.5 V) at low operation voltage (±8 V), good retention (>10 years), chemical and thermal stability (1000°C), as well as tunable memory performance employing with different tunneling layers. The fabrication of such memory structure is compatible with existing semiconductor processing thus has promise on low-cost integrated nanoscale memory applications.

Bipolar one diode-one resistor integration for high-density resistive memory applications.

Different from conventional unipolar-type 1D-1R RRAM devices, a bipolar-type 1D-1R memory device concept is proposed and successfully demonstrated by the integration of Ni/TiOx/Ti diode and Pt/HfO2/Cu bipolar RRAM cell to suppress the undesired sneak current in a cross-point array. The bipolar 1D-1R memory device not only achieves self-compliance resistive switching characteristics by the reverse bias current of the Ni/TiOx/Ti diode, but also exhibits excellent bipolar resistive switching characteristics such as uniform switching, satisfactory data retention, and excellent scalability, which give it high potentiality for high-density integrated nonvolatile memory applications.

A study of cycling induced degradation mechanisms in Si nanocrystal memory devices.

The endurance of Si nanocrystal memory devices under Fowler-Nordheim program and erase (P/E) cycling is investigated. Both threshold voltage (V(th)) and subthreshold swing (SS) degradation are observed when using a high program or erase voltage. The change of SS is found to be proportional to the shift of V(th), indicating that the generation of interface traps plays a dominant role. The charge pumping and the mid-gap voltage methods have been used to analyze endurance degradation both qualitatively and quantitatively. It is concluded that high erase voltage causes severe threshold voltage degradation by generating more interface traps and trapped oxide charges.

Controllable growth of nanoscale conductive filaments in solid-electrolyte-based ReRAM by using a metal nanocrystal covered bottom electrode.

Resistive memory (ReRAM) based on a solid-electrolyte insulator is a promising nanoscale device and has great potentials in nonvolatile memory, analog circuits, and neuromorphic applications. The underlying resistive switching (RS) mechanism of ReRAM is suggested to be the formation and rupture of nanoscale conductive filament (CF) inside the solid-electrolyte layer. However, the random nature of the nucleation and growth of the CF makes their formation difficult to control, which is a major obstacle for ReRAM performance improvement. Here, we report a novel approach to resolve this challenge by adopting a metal nanocrystal (NC) covered bottom electrode (BE) to replace the conventional ReRAM BE. As a demonstration vehicle, a Ag/ZrO(2)/Cu NC/Pt structure is prepared and the Cu NC covered Pt BE can control CF nucleation and growth to provide superior uniformity of RS properties. The controllable growth of nanoscale CF bridges between Cu NC and Ag top electrode has been vividly observed by transmission electron microscopy (TEM). On the basis of energy-dispersive X-ray spectroscopy (EDS) and elemental mapping analyses, we further confirm that the chemical contents of the CF are mainly Ag atoms. These testing/metrology results are consistent with the simulation results of electric-field distribution, showing that the electric field will enhance and concentrate on the NC sites and control location and orientation of Ag CFs.