A Novel Channel Preparation Scheme to Optimize Program Disturbance in Three-Dimensional NAND Flash Memory.

The program disturbance characteristics of three-dimensional (3D) vertical NAND flash cell array architecture pose a critical reliability challenge due to the lower unselected word line (WL) pass bias (Vpass) window. In other words, the key contradiction of program disturbance is that the operational Vpass during the program's performance cannot be too high or too low. For instance, the 3D NAND program's operation string needs a lower Vpass bias to suppress unselected WL Vpass bias-induced Fowler-Nordheim tunneling (FN tunneling), but for the inhibited string, the unselected WL needs a higher Vpass bias to suppress selected WL program bias (Vpgm)-induced FN tunneling. In this paper, a systematical insight into the relationship between the channel potential and channel electron density is given. Based on this intensive investigation, we studied a novel channel preparation scheme using "Gate-induced drain leakage (GIDL) pre-charge". Our methodology does not require the introduction of any new structures in 3D NAND, or changes in the operational Vpass bias. Instead, the potential on the unselected channel is enhanced by exploiting the holes generated by the GIDL operation effectively, leading to significantly suppressed program disturbance and a larger pass disturb window. To validate the effectiveness of the "GIDL pre-charge" method, TCAD simulation and real silicon data are used.

Investigation of Erase Cycling Induced Joint Dummy Cell Disturbance in Dual-Deck 3D NAND Flash Memory.

To satisfy the increasing demands for more word-line (WL) layers, the dual-deck even triple-deck architecture has emerged in 3D NAND Flash. However, the new reliability issues that occurred at the joint region of two decks became a severe challenge for developing multiple-deck technology. This work reported an abnormal reliability issue introduced by erasing disturbance of the dummy WLs at the joint region (Joint-DMYs) under multiple cycling. More specifically, after several erase cycling stresses, the increasing joint-DMY's threshold voltage (Vt) due to the operational stress will finally result in additional disturbance to the adjacent data WLs. In this paper, we proposed this disturbance during erase originates from the backward injected electrons through FN tunneling based on our TCAD simulation result. Moreover, we also proposed an optimal erase scheme to reduce the backward electron injection and suppress the abnormal joint-DMY disturbance during the erase cycling.

Investigation of the Connection Schemes between Decks in 3D NAND Flash.

Dual-deck stacking technology is an effective solution for solving the contradiction between the demand for increasing storage layers and the challenge of the deep hole etching process in 3D NAND flash. The connection scheme between decks is a key technology for the dual-deck structure. It has become one of the necessary techniques for 3D NAND flash storage density improvement. This article mainly studies the impact of connection schemes between decks on cell reliability. Based on experimental data and simulation analysis, unfavorable effects were found as the gate channeling the breakdown and data retention characteristics of the top cells in the lower deck deteriorated due to the local electric field enhancement in the connection scheme without a poly-plug. This mainly contributed to the structural change of these cells within process impact. They will suffer secondary etching during the upper deck channel etching process due to alignment issues between the upper and lower decks. In another scheme with a poly-plug connection between decks, the saturation current of the channel decreased and the current variation increased. The fundamental cause of the current anomaly is that the Poly-plug has a certain shielding effect on channel inversion and the weak inversion region becomes a bottleneck for the channel current. The increase in variation is due to the shielding effect differences in the different structures of the poly-plug. Therefore, for the connection scheme without a poly-plug, the article proposes to improve device reliability by increasing the oxide thickness between decks and setting the top cells of the lower decks to be virtual cells. For the connection scheme with a poly-plug, the plug's N-type doping scheme is proposed to avoid the current dropping anomaly.

A Novel Program Scheme for Z-Interference Improvement in 3D NAND Flash Memory.

With gate length (Lg) and gate spacing length (Ls) shrinkage, the cell-to-cell z-interference phenomenon is increasingly severe in 3D NAND charge-trap memory. It has become one of the key reliability concerns for 3D NAND cell scaling. In this work, z-interference mechanisms were investigated in the programming operation with the aid of Technology Computer-Aided Design (TCAD) and silicon data verification. It was found that the inter-cell trapped charges are one of the factors causing z-interference after cell programming, and these trapped charges can be modulated during programming. Thus, a novel program scheme is proposed to suppress the z-interference by reducing the pass voltage (Vpass) of the adjacent cells during programming. As a result, the proposed scheme suppresses the Vth shift of 40.1% for erased cells with Lg/Ls = 31/20 nm. In addition, this work further analyzes the optimization and balance of program disturbance and z-interference with the scaling of cell Lg-Ls based on the proposed scheme.