Hardware implementation of memristor-based artificial neural networks.

Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing, help alleviate the data communication bottleneck to some extent, but paradigm- shifting concepts are required. Memristors, a novel beyond-complementary metal-oxide-semiconductor (CMOS) technology, are a promising choice for memory devices due to their unique intrinsic device-level properties, enabling both storing and computing with a small, massively-parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. In this work we review the latest efforts for achieving hardware-based memristive artificial neural networks (ANNs), describing with detail the working principia of each block and the different design alternatives with their own advantages and disadvantages, as well as the tools required for accurate estimation of performance metrics. Ultimately, we aim to provide a comprehensive protocol of the materials and methods involved in memristive neural networks to those aiming to start working in this field and the experts looking for a holistic approach.

Recursive Threshold Logic-A Bioinspired Reconfigurable Dynamic Logic System With Crossbar Arrays.

The neuron behavioral models are inspired by the principle of the firing of neurons, and weighted accumulation of charge for a given set of input stimuli. Biological neurons show dynamic behavior through its feedback and feedforward time-dependent responses. The principle of the firing of neurons inspires threshold logic design by applying threshold functions on the weight summation of inputs. In this article, we present a recursive threshold logic unit that uses the output feedback from standard threshold logic gates to emulate Boolean expressions in a time-sequenced manner. The Boolean expression is implemented with an analog resistive divider in memristive crossbars and a hard-threshold function designed with CMOS comparator for realizing the sums (OR) and products (AND) operators. The method benefits from reliable programming of the memristors in 1T1R crossbar configuration to suppress sneak path currents and thus enable larger crossbar sizes, which in turn allow a higher number of Boolean inputs. The reference threshold voltage for the decision comparators is tuned to implement AND and OR logic. The threshold value range is limited by the number of inputs to the crossbar. Simultaneously, the resistance of the memristors is kept constant at RON. The circuit's tolerance to the memristor variability and aging are analyzed, showing sufficient resilience. Also, the proposed recursive logic uses fewer cross-points, and has lower power dissipation than other memristive logic and CMOS implementation.

Neuromemristive Circuits for Edge Computing: A Review.

The volume, veracity, variability, and velocity of data produced from the ever increasing network of sensors connected to Internet pose challenges for power management, scalability, and sustainability of cloud computing infrastructure. Increasing the data processing capability of edge computing devices at lower power requirements can reduce several overheads for cloud computing solutions. This paper provides the review of neuromorphic CMOS-memristive architectures that can be integrated into edge computing devices. We discuss why the neuromorphic architectures are useful for edge devices and show the advantages, drawbacks, and open problems in the field of neuromemristive circuits for edge computing.

Who is the Winner? Memristive-CMOS Hybrid Modules: CNN-LSTM Versus HTM.

Hierarchical, modular and sparse information processing are signature characteristics of biological neural networks. These aspects have been the backbone of several artificial neural network designs of the brain-like networks, including Hierarchical Temporal Memory (HTM). The main contribution of this work is showing that Convolutional Neural Network (CNN) in combination with Long short term memory (LSTM) can be a good alternative for implementing the hierarchy, modularity and sparsity of information processing. To demonstrate this, we draw a comparison of CNN-LSTM and HTM performance on a face recognition problem with a small training set. We also present the analog CMOS-memristor circuit blocks required to implement such a scheme. The presented memristive implementations of the CNN-LSTM architecture are easier to i mplement, train and offer higher recognition performance than the HTM. The study also includes memristor variability and failure analysis.