RESUMEN
Recent years have seen a resurgence of interest in crystalline silicon Schottky junction solar cells distinguished by the use of low density of electronic states (DOS) nanocarbons (nanotubes, graphene) as the metal contacting the Si. Recently, unprecedented modulation of the power conversion efficiency in a single material system has been demonstrated in such cells by the use of electronic gating. The gate field induced Fermi level shift in the low-DOS carbon serves to enhance the junction built-in potential, while a gate field induced inversion layer at the Si surface, in regions remote from the junction, keeps the photocarriers well separated there, avoiding recombination at surface traps and defects (a key loss mechanism). Here, we extend these results into the third dimension of a vertical Si nanowire array solar cell. A single wall carbon nanotube layer engineered to contact virtually each n-Si nanowire tip extracts the minority carriers, while an ionic liquid electrolytic gate drives the nanowire body into inversion. The enhanced light absorption of the vertical forest cell, at 100 mW/cm(2) AM1.5G illumination, results in a short-circuit current density of 35 mA/cm(2) and associated power conversion efficiency of 15%. These results highlight the use of local fields as opposed to surface passivation as a means of avoiding front surface recombination. A deleterious electrochemical reaction of the silicon due to the electrolyte gating is shown to be caused by oxygen/water entrained in the ionic liquid electrolyte. While encapsulation can avoid the issue, a nonencapsulation-based approach is also implemented.
RESUMEN
An improved process for graphene transfer was used to demonstrate high performance graphene enabled vertical organic field effect transistors (G-VFETs). The process reduces disorder and eliminates the polymeric residue that typically plagues transferred films. The method also allows for purposely creating pores in the graphene of a controlled areal density. Transconductance observed in G-VFETs fabricated with a continuous (pore-free) graphene source electrode is attributed to modulation of the contact barrier height between the graphene and organic semiconductor due to a gate field induced Fermi level shift in the low density of electronic-states graphene electrode. Pores introduced in the graphene source electrode are shown to boost the G-VFET performance, which scales with the areal pore density taking advantage of both barrier height lowering and tunnel barrier thinning. Devices with areal pore densities of 20% exhibit on/off ratios and output current densities exceeding 10(6) and 200 mA/cm(2), respectively, at drain voltages below 5 V.
