RESUMEN
The concept of three-dimensional stacking of device layers has attracted significant attention with the increasing difficulty in scaling down devices. Monolithic 3D (M3D) integration provides a notable benefit in achieving a higher connection density between upper and lower device layers than through-via-silicon. Nevertheless, the practical implementation of M3D integration into commercial production faces several technological challenges. Developing an upper active channel layer for device fabrication is the primary challenge in M3D integration. The difficulty arises from the thermal budget limitation for the upper channel process because a high thermal budget process may degrade the device layers below. This paper provides an overview of the potential technologies for forming active channel layers in the upper device layers of M3D integration, particularly for complementary metal-oxide-semiconductor devices and digital circuits. Techniques are for polysilicon, single crystal silicon, and alternative channels, which can solve the temperature issue for the top layer process.
RESUMEN
The effects of the grain size of Pt bottom electrodes on the ferroelectricity of hafnium zirconium oxide (HZO) were studied in terms of the orthorhombic phase transformation. HZO thin films were deposited by chemical solution deposition on the Pt bottom electrodes with various grain sizes which had been deposited by direct current sputtering. All the samples were crystallized by rapid thermal annealing at 700 °C to allow a phase transformation. The crystallographic phases were determined by grazing incidence X-ray diffraction, which showed that the bottom electrode with smaller Pt grains resulted in a larger orthorhombic phase composition in the HZO film. As a result, capacitors with smaller Pt grains for the bottom electrode showed greater ferroelectric polarization. The smaller grains produced larger in-plane stress which led to more orthorhombic phase transformation and higher ferroelectric polarization.
RESUMEN
This paper presents a straightforward, low-cost, and effective integration process for the fabrication of membrane gate thin film transistors (TFTs) with an air gap. The membrane gate TFT with an air gap can be used as the highly sensitive tactile force sensor. The suspended membrane gate with an air gap as the insulator layer is formed by multiple photolithography steps and photoresist sacrificial layers. The viscosity of the photoresist and the spin speed was used to modify the thickness of the air gap during the coating process. The tactile force was measured by monitoring the drain current of the TFT as the force changed the thickness of the air gap. The sensitivity of the devices was enhanced by an optimal gate size and low Young's modulus of the gate material. This simple process has the potential for the production of small, versatile, and highly sensitive sensors.
RESUMEN
Nickel silicide (NiSi) is commonly used as a contact material for metal junctions but the poor thermal instability of NiSi above 600 °C has limited the further scaling down of devices and the implementation of novel schemes, such as monolithic 3-dimensional integration. This paper suggests a process to improve the thermal stability of NiSi through nitrogen incorporation during the silicidation process. The optimal level of nitrogen incorporation in NiSi reduced the nickel diffusion rate and enhanced the thermal stability by preventing the formation of a nickel disilicide phase. On the other hand, a higher level of N incorporation led to Ni3N formation, which impeded the complete transformation to NiSi. Therefore, it is essential to incorporate the optimal content of N. In this study, NiSi with 3.9% N incorporation showed superior electrical characteristics, such as the sheet resistance, junction leakage, and stable Schottky barrier height, even after high-temperature post silicidation annealing at 600 °C for 30 min.