Two-Dimensional Tunneling Memtransistor with Thin-Film Heterostructure for Low-Power Logic-in-Memory Complementary Metal-Oxide Semiconductor.

With the demand for high-performance and miniaturized semiconductor devices continuously rising, the development of innovative tunneling transistors via efficient stacking methods using two-dimensional (2D) building blocks has paramount importance in the electronic industry. Hence, 2D semiconductors with atomically thin geometries hold significant promise for advancements in electronics. In this study, we introduced tunneling memtransistors with a thin-film heterostructure composed of 2D semiconducting MoS2 and WSe2. Devices with the dual function of tuning and memory operation were realized by the gate-regulated modulation of the barrier height at the heterojunction and manipulation of intrinsic defects within the exfoliated nanoflakes using solution processes. Further, our investigation revealed extensive edge defects and four distinct defect types, namely monoselenium vacancies, diselenium vacancies, tungsten vacancies, and tungsten adatoms, in the interior of electrochemically exfoliated WSe2 nanoflakes. Additionally, we constructed complementary metal-oxide semiconductor-based logic-in-memory devices with a small static power in the range of picowatts using the developed tunneling memtransistors, demonstrating a promising approach for next-generation low-power nanoelectronics.

Selenium-alloyed tellurium oxide for amorphous p-channel transistors.

Compared to polycrystalline semiconductors, amorphous semiconductors offer inherent cost-effective, simple and uniform manufacturing. Traditional amorphous hydrogenated Si falls short in electrical properties, necessitating the exploration of new materials. The creation of high-mobility amorphous n-type metal oxides, such as a-InGaZnO (ref. 1), and their integration into thin-film transistors (TFTs) have propelled advancements in modern large-area electronics and new-generation displays2-8. However, finding comparable p-type counterparts poses notable challenges, impeding the progress of complementary metal-oxide-semiconductor technology and integrated circuits9-11. Here we introduce a pioneering design strategy for amorphous p-type semiconductors, incorporating high-mobility tellurium within an amorphous tellurium suboxide matrix, and demonstrate its use in high-performance, stable p-channel TFTs and complementary circuits. Theoretical analysis unveils a delocalized valence band from tellurium 5p bands with shallow acceptor states, enabling excess hole doping and transport. Selenium alloying suppresses hole concentrations and facilitates the p-orbital connectivity, realizing high-performance p-channel TFTs with an average field-effect hole mobility of around 15 cm2 V-1 s-1 and on/off current ratios of 106-107, along with wafer-scale uniformity and long-term stabilities under bias stress and ambient ageing. This study represents a crucial stride towards establishing commercially viable amorphous p-channel TFT technology and complementary electronics in a low-cost and industry-compatible manner.

All-Solution-Processed High-Performance MoS2 Thin-Film Transistors with a Quasi-2D Perovskite Oxide Dielectric.

Assembling solution-processed van der Waals (vdW) materials into thin films holds great promise for constructing large-scale, high-performance thin-film electronics, especially at low temperatures. While transition metal dichalcogenide thin films assembled in solution have shown potential as channel materials, fully solution-processed vdW electronics have not been achieved due to the absence of suitable dielectric materials and high-temperature processing. In this work, we report on all-solution-processedvdW thin-film transistors (TFTs) comprising molybdenum disulfides (MoS2) as the channel and Dion-Jacobson-phase perovskite oxides as the high-permittivity dielectric. The constituent layers are prepared as colloidal solutions through electrochemical exfoliation of bulk crystals, followed by sequential assembly into a semiconductor/dielectric heterostructure for TFT construction. Notably, all fabrication processes are carried out at temperatures below 250 °C. The fabricated MoS2 TFTs exhibit excellent device characteristics, including high mobility (>10 cm2 V-1 s-1) and an on/off ratio exceeding 106. Additionally, the use of a high-k dielectric allows for operation at low voltage (∼5 V) and leakage current (∼10-11 A), enabling low power consumption. Our demonstration of the low-temperature fabrication of high-performance TFTs presents a cost-effective and scalable approach for heterointegrated thin-film electronics.