NeuroBus - Architecture for an Ultra-Flexible Neural Interface.

This article presents the system architecture for an implant concept called NeuroBus. Tiny distributed direct digitizing neural recorder ASICs on an ultra-flexible polyimide substrate are connected in a bus-like structure, allowing short connections between electrode and recording front-end with low wiring effort and high customizability. The small size (344 µm × 294 µm) of the ASICs and the ultraflexible substrate allow a low bending stiffness, enabling the implant to adapt to the curvature of the brain and achieving high structural biocompatibility. We introduce the architecture, the integrated building blocks, and the post-CMOS processes required to realize a NeuroBus, and we characterize the prototyped direct digitizing neural recorder front-end as well as polyimide-based ECoG brain interface. A rodent animal model is further used to validate the joint capability of the recording front-end and thin-film electrode array.

Highly conformable chip-in-foil implants for neural applications.

Demands for neural interfaces around functionality, high spatial resolution, and longevity have recently increased. These requirements can be met with sophisticated silicon-based integrated circuits. Embedding miniaturized dice in flexible polymer substrates significantly improves their adaptation to the mechanical environment in the body, thus improving the systems' structural biocompatibility and ability to cover larger areas of the brain. This work addresses the main challenges in developing a hybrid chip-in-foil neural implant. Assessments considered (1) the mechanical compliance to the recipient tissue that allows a long-term application and (2) the suitable design that allows the implant's scaling and modular adaptation of chip arrangement. Finite element model studies were performed to identify design rules regarding die geometry, interconnect routing, and positions for contact pads on dice. Providing edge fillets in the die base shape proved an effective measure to improve die-substrate integrity and increase the area available for contact pads. Furthermore, routing of interconnects in the immediate vicinity of die corners should be avoided, as the substrate in these areas is prone to mechanical stress concentration. Contact pads on dice should be placed with a clearance from the die rim to avoid delamination when the implant conforms to a curvilinear body. A microfabrication process was developed to transfer, align, and electrically interconnect multiple dice into conformable polyimide-based substrates. The process enabled arbitrary die shape and size over independent target positions on the conformable substrate based on the die position on the fabrication wafer.

A Direct Digitizing Chopped Neural Recorder Using a Body-Induced Offset Based DC Servo Loop.

This article presents a direct digitizing neural recorder that uses a body-induced offset based DC servo loop to cancel electrode offset (EDO) on-chip. The bulk of the input pair is used to create an offset, counteracting the EDO. The architecture does not require AC coupling capacitors which enables the use of chopping without impedance boosting while maintaining a large input impedance of 238 M Ω over the whole 10 kHz bandwidth. Implemented in a 180 nm HV-CMOS process, the prototype occupies a silicon area of only 0.02 mm2 while consuming 12.8 µW and achieving 1.82 µV[Formula: see text] of input-referred noise in the local field potential (LFP) band and a NEF of 5.75.

A Chopped Neural Front-End Featuring Input Impedance Boosting With Suppressed Offset-Induced Charge Transfer.

Modern neuromodulation systems typically provide a large number of recording and stimulation channels, which reduces the available power and area budget per channel. To maintain the necessary input-referred noise performance despite growingly rigorous area constraints, chopped neural front-ends are often the modality of choice, as chopper-stabilization allows to simultaneously improve (1/f) noise and area consumption. The resulting issue of a drastically reduced input impedance has been addressed in prior art by impedance boosters based on voltage buffers at the input. These buffers precharge the large input capacitors, reduce the charge drawn from the electrodes and effectively boost the input impedance. Offset on these buffers directly translates into charge-transfer to the electrodes, which can accelerate electrode aging. To tackle this issue, a voltage buffer with ultra-low time-averaged offset is proposed, which cancels offset by periodic reconfiguration, thereby minimizing unintended charge transfer. This article explains the background and circuit design in detail and presents measurement results of a prototype implemented in a 180 nm HV CMOS process. The measurements confirm that signal-independent, buffer offset induced charge transfer occurs and can be mitigated by the presented buffer reconfiguration without adversely affecting the operation of the input impedance booster. The presented neural recorder front-end achieves state of the art performance with an area consumption of 0.036 mm2, an input referred noise of [Formula: see text] (1 to 200 Hz) and [Formula: see text] (0.2 to 10 kHz), power consumption of 13.7 µW from 1.8 V supply, as well as CMRR and PSRR ≥ 83 dB at 50 Hz.

Study of Compressed Sensing and Predictor Techniques for the Compression of Neural Signals under the Influence of Noise.

In this paper an analysis of compression schemes based on compressed sensing (CS) and predictor techniques for neural signals is presented. The focus is on how much a compression algorithm can reduce data while not affecting the subsequent signal processing. Since neural signals are processed by means of spike sorting algorithms the evaluation is not trivial and not well defined, since there exists in fact many different ways to detect and cluster the spikes. Evaluating how much a compression scheme affects the result of spike sorting programs is a crucial step before implementing such compression technique. In the analysis two use cases are evaluated: in the first, spikes are detected and extracted and only thereafter compressed. In the second case, no information on the spikes is available and the whole raw signal is compressed. When dealing only with spike frames CS offers great compression at almost no loss, in the case of the whole recording its performances are greatly impaired and delta compression outperforms it in terms of data reduction and spike sorting results. In this case the reduction rates are modest but significant, ≈3 - 4 times data reduction and the whole signal is preserved avoiding big permanent losses of information.

A miniaturized UWB antenna for implantable data telemetry.

This paper presents a miniaturized impulse radio ultra-wideband (IR-UWB) antenna which is designed for transcutaneous, short-distance data communication used in multichannel neural recording. In these systems, with the increasing number of recording channels, data rates of 10-100 Mbit/s must be transmitted with very limited power and area. Therefore, the antennas are designed as planar, ellipsoidal dipoles on a high permittivity substrate with εr = 10.2 to achieve high radiation efficiency with small physical size. In order to increase the robustness against misalignment, a circularly polarized antenna is used at the external receiver unit, reducing the signal power variation under angular misalignment. For the transmitting antenna a miniaturized prototype with an integrated pulse generator was designed on a round shaped PCB with a diameter of only 14mm. Measurements through porcine skin in the frequency domain show an attenuation of less than 30dB in the intended frequency band between 6 and 8.5GHz. Additional evaluations in the time domain prove possible pulse repetition rates of up to 100MHz at a transmission distance of 1.5cm.

Evaluation of logarithmic vs. linear ADCs for neural signal acquisition and reconstruction.

An evaluation of the effectiveness of logarithmic quantization for neural signals is performed in this paper. Logarithmic analog to digital converters (ADCs) are employed in biomedical applications where signals with high dynamic range are recorded. For the same number of bits of a linear ADC, a logarithmic one can better resolve smaller signals, at a price of worse accuracy for high amplitudes. This feature can also reduce the number of bits required and then allow data reduction as well. No study was done to verify the efficacy of such ADCs on neural signals in the context of spike sorting. Using simulated and recorded publically available data this is done extensively in the paper. Neural signals are quantized with linear and logarithmic ADCs. Then using the original signal as reference, the new signals are processed with Osort for automated spike sorting. The results are compared with the reference to determine whether one of the two quantization methods provides some benefits. The result is that logarithmic ADCs outperform linear quantization only in the range from 2 to 5 bits. Such low resolutions are unfortunately not enough for proper spike sorting, hence logarithmic ADCs appear not to provide an improvement over a conventional ADC.

A low-power high-sensitivity single-chip receiver for NMR microscopy.

In this paper, we present a fully-integrated receiver for NMR microscopy applications manufactured in a 0.13µm CMOS technology. The design co-integrates a 10-turn planar detection coil together with a complete quadrature, low-IF downconversion receiver on a single chip, which operates from a single 1.5V supply with a total power dissipation of 18mW. The detector's measured time-domain spin sensitivity is 3×10(13)(1)Hspins/Hz at 7T. Additionally, the paper discusses two important aspects of NMR microscopy using planar detection coils: the link between the detection coil's spin sensitivity and the achievable image SNR and the correction of image artifacts induced by the inhomogeneous sensitivity profile of planar detection coils. More specifically, we derive analytical expressions for both the theoretical image SNR as a function of the coil's spin sensitivity and the sensitivity correction for a known coil sensitivity profile in CTI MR imaging experiments. Both expressions are validated using measured data in the imaging section of the paper. Thanks to the improved spin sensitivity of the utilized integrated receiver chip compared to a previously presented design, we were able to obtain sensitivity corrected images in a 7T spectroscopy magnet with isotropic resolutions of 9.6µm and 5µm with single-shot SNRs of 37 and 15 in relatively short imaging times of 4.4h and 24h, respectively.

Single-cycle-PLL detection for real-time FM-AFM applications.

In this paper we present a novel architecture for phase-locked loop (PLL) based high-speed demodulation of frequency-modulated (FM) atomic force microscopy (AFM) signals. In our approach, we use single-sideband (SSB) frequency upconversion to translate the AFM signal from the position sensitive detector to a fixed intermediate frequency (IF) of 10 MHz. In this way, we fully benefit from the excellent noise performance of PLL-based FM demodulators still avoiding the intrinsic bandwidth limitation of such systems. In addition, the upconversion to a fixed IF renders the PLL demodulator independent of the cantilever's resonance frequency, allowing the system to work with a large range of cantilever frequencies. To investigate if the additional noise introduced by the SSB upconverter degrades the system noise figure we present a model of the AM-to-FM noise conversion in PLLs incorporating a phase-frequency detector. Using this model, we can predict an upper corner frequency for the demodulation bandwidth above which the converted noise from the single-sideband upconverter becomes the dominant noise source and therefore begins to deteriorate the overall system performance. The approach is validated by both electrical and AFM measurements obtained with a PCB-based prototype implementing the proposed demodulator architecture.

Recent advances in power efficient output stage for high density implantable stimulators.

A major drawback of a current-controlled stimulation is its power efficiency. However, it is commonly used in implantable stimulators due to its safety. The power efficiency of a current-controlled stimulation can be improved by reducing the headroom voltage needed in the current driver. A promising technique is to bias the transistor in triode region whereas improving output impedance through the regulated cascode structure. This comes with a feature of implicit compliance monitor which is used for the supply voltage adaptation. This paper presents an overview on recent power efficient high voltage-compliance output drivers.

A 232-channel retinal vision prosthesis with a miniaturized hermetic package.

Miniaturization of implantable devices while drastically increasing the number of stimulation channels is one of the greatest challenges in implant manufacturing because a small but hermetic package is needed that provides reliable protection for the electronics over decades. Retinal vision prostheses are the best example for it. This paper presents a miniaturized 232-channel vision prosthesis, summarizing the studies on the individual technologies that were developed, improved and combined to fabricate a telemetrically powered retinal device sample. The implantable unit, which is made out of a high temperature co-fired alumina ceramic package containing hermetic feedthroughs, electronic circuitry and a radio frequency coil for powering is manufactured through a modified screen-printing/lasering process. The package is sealed with solder glass to provide unaffected inductive coupling to the telemetric transmitter. A 0.05 cc inner volume allows helium leak testing and mathematical lifetime estimations for moisture-induced failure of up to 100 years. The feedthroughs contact a thin-film polyimide electrode array that utilizes DLC and SiC coatings for improved interlayer adhesion of the metallic tracks to the polymer carrier. Two metal layers allow integrated wiring of the electrode array within the very limited space.

Evaluation study of compressed sensing for neural spike recordings.

In this paper, an evaluation study of compressed sensing (CS) for neural action potential (spike) signals in MATLAB is presented. State-of-the-art neural recorders use 100 or more parallel channels to measure neural activity resulting in a data rate of 16 - 20 Mbit/s. Since a low-power design is required for an implanted neural recorder, it seems advantageous to compress the neural data prior to the wireless transmission. The continuous neural spike signals are compressed and transmitted to facilitate the possibility of an unrestricted data analysis at the receiver. Synthesized and recorded neural data sets are used to test the performance of CS. The 6-level Daubechies-8 wavelet decomposition matrix and two learned dictionary matrices are utilized as dictionaries for CS. The compression results are evaluated with the spike sorting program OSort. CS is shown to work for the compression of low-noise synthesized neural spike signals with a compression rate of 2.05, but cannot be recommended for the compression of neural spike signals in general.

Optical transcutaneous link for low power, high data rate telemetry.

A low power and high data rate wireless optical link for implantable data transmission is presented in this paper. In some neural prosthetic applications particularly in regard to neural recording system, there is a demand for high speed communication between an implanted device and an external device. An optical transcutaneous link is a promising implantable telemetry solution, since it shows lower power requirements than RF telemetry. In this paper, this advantage is further enhanced by using a modified on-off keying and a simple custom designed low power VCSEL driver. This transmitter achieves an optical transcutaneous link capable of transmitting data at 50 Mbps through the 4 mm tissue, with a tolerance of 2 mm misalignment and a BER of less than 10(-5), while the power consumption is only 4.1 mW or less.

Distributed clock gating for power reduction of a programmable waveform generator for neural stimulation.

This paper describes how to employ distributed clock gating to achieve an overall low power design of a programmable waveform generator intended for a neural stimulator. The power efficiency is enabled using global timing control combined with local amplitude distribution over a bus to the local stimulator frontends. This allows the combination of local and global clock gating for complete sub-blocks of the design. A counter and a shifter employed at the local digital stimulator reduce the design complexity for the waveform generation and thus the overall power consumptions. The average power results indicate that 63% power can be saved for the global stimulator control unit and 89-96% power can be saved for the local digital stimulator by using the proposed approach. The circuit has been implemented and successfully tested in a 0.35 µm AMS HVCMOS technology.

An architecture for a universal neural stimulator with almost arbitrary current waveform.

This paper describes the architecture and protocol of a digital stimulator which is intended to realize a highly flexible stimulation waveform pattern. The flexibility is provided by programmable stimulation profiles such as pulse duration, frequency, polarity, amplitude level, arbitrary wave shape, train of pulses and different types of wave patterns among stimulation sites. The programmable stimulation data is therefore divided into two parts, global and local stimulation data. The global data which defines the timing of pulse duration and wave shaping, are sent sequentially to all stimulation sites using 5-bit control commands. Local stimulation data defines the initial amplitude setting and is stored at each active stimulation cell. At each stimulation site, the amplitude level can be changed during the stimulation process and consequently it generates an arbitrary wave shape. Without the need of a large memory size, the proposed simple design architecture generates not only arbitrary stimulation waveforms, but also trains of pulses as well as different types of stimulation patterns among stimulation sites are enabled.

An active approach for charge balancing in functional electrical stimulation.

Charge balancing is a major concern in functional electrical stimulation, since any excess charge accumulation over time leads to electrolysis with electrode dissolution and tissue destruction. This paper presents a new active approach for charge balancing using long-term offset regulation. Therefore, the electrode voltage is briefly monitored after each stimulation cycle and checked if it remains within a predefined voltage range. If not, an offset current is adjusted in order to track the biphasic current mismatch in upcoming stimulations. This technique is compared to a previously introduced active charge balancer as well as commonly used passive balancing techniques. Subsequently, the techniques are verified through experiments on a platinum black electrode in 0.9% saline solution.

Recent advances in charge balancing for functional electrical stimulation.

Charge balancing is a major concern in functional electrical stimulation, since any excess charge accumulation over time leads to electrolysis with electrode dissolution and tissue destruction. Its major function is to ensure that the mean value of electrode voltage is kept within a safe level. However, it serves as a failure protection as well. This paper presents an overview on recent advances in this field, both passive and active (closed-loop) charge balancing techniques.