Efficient Hybrid Training Method for Neuromorphic Hardware Using Analog Nonvolatile Memory.

Neuromorphic hardware using nonvolatile analog synaptic devices provides promising advantages of reducing energy and time consumption for performing large-scale vector-matrix multiplication (VMM) operations. However, the reported training methods for neuromorphic hardware have appreciably shown reduced accuracy due to the nonideal nature of analog devices, and use conductance tuning protocols that require substantial cost for training. Here, we propose a novel hybrid training method that efficiently trains the neuromorphic hardware using nonvolatile analog memory cells, and experimentally demonstrate the high performance of the method using the fabricated hardware. Our training method does not rely on the conductance tuning protocol to reflect weight updates to analog synaptic devices, which significantly reduces online training costs. When the proposed method is applied, the accuracy of the hardware-based neural network approaches to that of the software-based neural network after only one-epoch training, even if the fabricated synaptic array is trained for only the first synaptic layer. Also, the proposed hybrid training method can be efficiently applied to low-power neuromorphic hardware, including various types of synaptic devices whose weight update characteristics are extremely nonlinear. This successful demonstration of the proposed method in the fabricated hardware shows that neuromorphic hardware using nonvolatile analog memory cells becomes a more promising platform for future artificial intelligence.

Medium-Temperature-Oxidized GeOx Resistive-Switching Random-Access Memory and Its Applicability in Processing-in-Memory Computing.

Processing-in-memory (PIM) is emerging as a new computing paradigm to replace the existing von Neumann computer architecture for data-intensive processing. For the higher end-user mobility, low-power operation capability is more increasingly required and components need to be renovated to make a way out of the conventional software-driven artificial intelligence. In this work, we investigate the hardware performances of PIM architecture that can be presumably constructed by resistive-switching random-access memory (ReRAM) synapse fabricated with a relatively larger thermal budget in the full Si processing compatibility. By introducing a medium-temperature oxidation in which the sputtered Ge atoms are oxidized at a relatively higher temperature compared with the ReRAM devices fabricated by physical vapor deposition at room temperature, higher device reliability has been acquired. Based on the empirically obtained device parameters, a PIM architecture has been conceived and a system-level evaluations have been performed in this work. Considerations include the cycle-to-cycle variation in the GeOx ReRAM synapse, analog-to-digital converter resolution, synaptic array size, and interconnect latency for the system-level evaluation with the Canadian Institute for Advance Research-10 dataset. A fully Si processing-compatible and robust ReRAM synapse and its applicability for PIM are demonstrated.

Highly-packed self-assembled graphene oxide film-integrated resistive random-access memory on a silicon substrate for neuromorphic application.

Resistive random-access memories (RRAMs) based on metal-oxide thin films have been studied extensively for application as synaptic devices in neuromorphic systems. The use of graphene oxide (GO) as a switching layer offers an exciting alternative to other materials such as metal-oxides. We present a newly developed RRAM device fabricated by implementing highly-packed GO layers on a highly doped Si wafer to yield a gradual modulation of the memory as a function of the number of input pulses. By using flow-enabled self-assembly, highly uniform GO thin films can be formed on flat Si wafers in a rapid and simple process. The switching mechanism was explored through proposed scenarios reconstructing the density change of the sp2cluster in the GO layer, resulting in a gradual conductance modulation. We analyzed that the current in a low resistance state could flow by tunneling or hopping via clusters because the distance between the sp2clusters in closely-packed GO layers is short. Finally, through a pattern-recognition simulation with a Modified National Institute of Standards and Technology database, the feasibility of using close-packed GO layers as synapse devices was successfully demonstrated.

Synergistic improvement of sensing performance in ferroelectric transistor gas sensors using remnant polarization.

Gaseous pollutants, including nitrogen oxides, pose a severe threat to ecosystems and human health; therefore, developing reliable gas-sensing systems to detect them is becoming increasingly important. Among the various options, metal-oxide-based gas sensors have attracted attention due to their capability for real-time monitoring and large response. In particular, in the field of materials science, there has been extensive research into controlling the morphological properties of metal oxides. However, these approaches have limitations in terms of controlling the response, sensitivity, and selectivity after the sensing material is deposited. In this study, we propose a novel method to improve the gas-sensing performance by utilizing the remnant polarization of ferroelectric thin-film transistor (FeTFT) gas sensors. The proposed FeTFT gas sensor has IGZO and HZO as the conducting channel and ferroelectric layer, respectively. It is demonstrated that the response and sensitivity of FeTFT gas sensors can be modulated by engineering the polarization of the ferroelectric layer. The amount of reaction sites in IGZO, including electrons and oxygen vacancy-induced negatively charged oxygen, is changed depending on upward and downward polarization. The results of this study provide an essential foundation for further development of gas sensors with tunable sensing properties.

Comprehensive and accurate analysis of the working principle in ferroelectric tunnel junctions using low-frequency noise spectroscopy.

Recently, ferroelectric tunnel junctions (FTJs) have gained extensive attention as possible candidates for emerging memory and synaptic devices for neuromorphic computing. However, the working principles of FTJs remain controversial despite the importance of understanding them. In this study, we demonstrate a comprehensive and accurate analysis of the working principles of a metal-ferroelectric-dielectric-semiconductor stacked FTJ using low-frequency noise (LFN) spectroscopy. In contrast to resistive random access memory, the 1/f noise of the FTJ in the low-resistance state (LRS) is approximately two orders of magnitude larger than that in the high-resistance state (HRS), indicating that the conduction mechanism in each state differs significantly. Furthermore, the factors determining the conduction of the FTJ in each state are revealed through a systematic investigation under various conditions, such as varying the electrical bias, temperature, and bias stress. In addition, we propose an efficient method to decrease the LFN of the FTJ in both the LRS and HRS using high-pressure forming gas annealing.

Analytically and empirically consistent characterization of the resistive switching mechanism in a Ag conducting-bridge random-access memory device through a pseudo-liquid interpretation approach.

A new physical analysis of the filament formation in a Ag conducting-bridge random-access memory (CBRAM) device in consideration of the existence of inter-atomic attractions caused by metal bonding is suggested. The movement of Ag atoms inside the switching layer is characterized hydrodynamically using the Young-Laplace equation during set and reset operations. Both meridional and azimuthal curvatures of the Ag filament protruding from the Ag electrode are accurately calculated to track down the exact shape of the Ag filament with change in the applied voltage. The second-order partial differential equation for the Ag filament geometry is derived from the equation of equilibrium between the electrostatic pressure and the Laplace one. The solution to the equation is numerically obtained, and furthermore, the abrupt set operation in the forming process, bipolar resistive-switching, and the threshold switching operation in the reset operations are successfully simulated in accordance with the numerical solutions. Also, it is demonstrated that the currents extracted from the suggested model show good agreement with the I-V characteristics measured from the fabricated Ag CBRAM device.

A novel physical unclonable function (PUF) using 16 × 16 pure-HfOxferroelectric tunnel junction array for security applications.

As the computing paradigm has shifted toward edge computing, improving the security of edge devices is attracting significant attention. However, because edge devices have limited resources in terms of power and area, it is difficult to apply a conventional cryptography system to protect them. On the other hand, as a simple security application, a physical unclonable function (PUF) can be implemented without power and area problems because it provides a security key by utilizing process variations without additional external circuits. Ferroelectric tunnel junctions (FTJs) are 2-terminal devices that store information by changing the resistance of a ferroelectric material, where the resistance is determined by the polarization states of the ferroelectric domains. Because polycrystalline ferroelectric materials have a multi-domain nature, domain variation can also be used as a randomness source to induce cell-to-cell variations along with process variations. In this paper, we demonstrate PUF operations of a low-power, small area 16 × 16 hafnium oxide (pure-HfOx)-based FTJ array using certain metrics. It is clear that the proposed array consisting of scaled FTJs has adequate randomness for security applications such that the array-level PUF operations are robust against model-based machine learning attacks.

Interlayer engineering for enhanced ferroelectric tunnel junction operations in HfOx-based metal-ferroelectric-insulator-semiconductor stack.

Ferroelectric tunnel junction (FTJ) has been considered as a promising candidate for next-generation memory devices due to its non-destructive and low power operations. In this article, we demonstrate the interlayer (IL) engineering in the FTJs to boost device performances. Through the analysis on the material and electrical characteristics of the fabricated FTJs with engineered IL stacks, it is clearly found that the insertion of an Al2O3layer between the SiO2insulator and the pure-HfOxFE improves the read disturbance (2Vc = 2.2 V increased), the endurance characteristics (tenfold improvement), and the cell-to-cell TER variation simultaneously without the degradation of the ferroelectricity (less than 5%) and the polarization switching speeds through grain size modulation. Based on these investigations, the guidelines of IL engineering for low power ferroelectric devices were provided to obtain stable and fast memory operations.

Effect of charge storage engineering on the NO2 gas sensing properties of a WO3 FET-type gas sensor with a horizontal floating-gate.

In this paper, we investigate the effects of charge storage engineering (CSE) on the NO2 gas sensing properties such as response, recovery, and sensitivity of a FET-type gas sensor with a horizontal floating-gate (FG) having tungsten trioxide (WO3) as a sensing layer. When the FET transducer is set at an erase state (ΔVth = -2 V), the holes injected into the FG by Fowler-Nordheim (F-N) tunneling increase the electron concentration at the WO3-passivation layer interface. Accordingly, an oxidizing gas, NO2, can take more electrons from WO3, which increases the change in the FG voltage (ΔVFG) by a factor of 2.4. Also, the recovery speed of the sensor in the erase state can be improved by applying pre-bias (Vpre) which is larger than the read bias (Vread). As the carriers in the WO3 film that can interact with NO2 increase by the excess holes stored in the FG by the erase operation, the sensitivity of the sensor also increases 3.2 times. The effects of CSE on various sensing performances are explained using energy band diagrams.

Retention Enhancement in Low Power NOR Flash Array with High-κ-Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide.

For improving retention characteristics in the NOR flash array, aluminum oxide (Al2O3, alumina) is utilized and incorporated as a tunneling layer. The proposed tunneling layers consist of SiO2/Al2O3/SiO2, which take advantage of higher permittivity and higher bandgap of Al2O3 compared to SiO2 and silicon nitride (Si3N4). By adopting the proposed tunneling layers in the NOR flash array, the threshold voltage window after 10 years from programming and erasing (P/E) was improved from 0.57 V to 4.57 V. In order to validate our proposed device structure, it is compared to another stacked-engineered structure with SiO2/Si3N4/SiO2 tunneling layers through technology computer-aided design (TCAD) simulation. In addition, to verify that our proposed structure is suitable for NOR flash array, disturbance issues are also carefully investigated. As a result, it has been demonstrated that the proposed structure can be successfully applied in NOR flash memory with significant retention improvement. Consequently, the possibility of utilizing HfO2 as a charge-trapping layer in NOR flash application is opened.

3-bit multilevel operation with accurate programming scheme in TiOx/Al2O3memristor crossbar array for quantized neuromorphic system.

As interest in artificial intelligence (AI) and relevant hardware technologies has been developed rapidly, algorithms and network structures have become significantly complicated, causing serious power consumption issues because an enormous amount of computation is required. Neuromorphic computing, a hardware AI technology with memory devices, has emerged to solve this problem. For this application, multilevel operations of synaptic devices are important to imitate floating point weight values in software AI technologies. Furthermore, weight transfer methods to desired weight targets must be arranged for off-chip training. From this point of view, we fabricate 32 × 32 memristor crossbar array and verify the 3-bit multilevel operations. The programming accuracy is verified for 3-bit quantized levels by applying a reset-voltage-control programming scheme to the fabricated TiOx/Al2O3-based memristor array. After that, a synapse composed of two differential memristors and a fully-connected neural network for modified national institute of standards and technology (MNIST) pattern recognition are constructed. The trained weights are post-training quantized in consideration of the 3-bit characteristics of the memristor. Finally, the effect of programming error on classification accuracy is verified based on the measured data, and we obtained 98.12% classification accuracy for MNIST data with the programming accuracy of 1.79% root-mean-square-error. These results imply that the proposed reset-voltage-control programming scheme can be utilized for a precise tuning, and expected to contribute for the development of a neuromorphic system capable of highly precise weight transfer.

Low-Latency Spiking Neural Networks Using Pre-Charged Membrane Potential and Delayed Evaluation.

Spiking neural networks (SNNs) have attracted many researchers' interests due to its biological plausibility and event-driven characteristic. In particular, recently, many studies on high-performance SNNs comparable to the conventional analog-valued neural networks (ANNs) have been reported by converting weights trained from ANNs into SNNs. However, unlike ANNs, SNNs have an inherent latency that is required to reach the best performance because of differences in operations of neuron. In SNNs, not only spatial integration but also temporal integration exists, and the information is encoded by spike trains rather than values in ANNs. Therefore, it takes time to achieve a steady-state of the performance in SNNs. The latency is worse in deep networks and required to be reduced for the practical applications. In this work, we propose a pre-charged membrane potential (PCMP) for the latency reduction in SNN. A variety of neural network applications (e.g., classification, autoencoder using MNIST and CIFAR-10 datasets) are trained and converted to SNNs to demonstrate the effect of the proposed approach. The latency of SNNs is successfully reduced without accuracy loss. In addition, we propose a delayed evaluation method (DE), by which the errors during the initial transient are discarded. The error spikes occurring in the initial transient is removed by DE, resulting in the further latency reduction. DE can be used in combination with PCMP for further latency reduction. Finally, we also show the advantages of the proposed methods in improving the number of spikes required to reach a steady-state of the performance in SNNs for energy-efficient computing.

Realization of Biomimetic Synaptic Functions in a One-Cell Organic Resistive Switching Device Using the Diffusive Parameter of Conductive Filaments.

Toward the successful development of artificial intelligence, artificial synapses based on resistive switching devices are essential ingredients to perform information processing in spiking neural networks. In neural processes, synaptic plasticity related to the history of neuron activity plays a critical role during learning. In resistive switching devices, it is barely possible to emulate both short-term plasticity and long-term plasticity due to the uncontrollable dynamics of the conductive filaments (CFs). Despite extensive effort to realize synaptic plasticity in such devices, it is still challenging to achieve reliable synaptic functions due to the overgrowth of CFs in a random fashion. Herein, we propose an organic resistive switching device with bio-realistic synaptic functions by adjusting the CF diffusive parameter. In the proposed device, complete synaptic plasticity provides the history-dependent change in the conductance. Moreover, the homeostatic feedback, which resembles the biological process, regulates CF growth in our device, which enhances the reliability of synaptic plasticity. This novel concept for realizing synaptic functions in organic resistive switching devices may provide a physical platform to advance the fundamental understanding of learning and memory mechanisms and develop a variety of neural circuits and neuromorphic systems that can be linked to artificial intelligence and next-generation computing paradigm.

3D AND-Type Stacked Array for Neuromorphic Systems.

NOR/AND flash memory was studied in neuromorphic systems to perform vector-by-matrix multiplication (VMM) by summing the current. Because the size of NOR/AND cells exceeds those of other memristor synaptic devices, we proposed a 3D AND-type stacked array to reduce the cell size. Through a tilted implantation method, the conformal sources and drains of each cell could be formed, with confirmation by a technology computer aided design (TCAD) simulation. In addition, the cell-to-cell variation due to the etch slope could be eliminated by controlling the deposition thickness of the cells. The suggested array can be beneficial in simple program/inhibit schemes given its use of Fowler-Nordheim (FN) tunneling because the drain lines and source lines are parallel. Therefore, the conductance of each synaptic device can be updated at low power level.

Proposition of deposition and bias conditions for optimal signal-to-noise-ratio in resistor- and FET-type gas sensors.

In the field of gas sensor studies, most researchers are focusing on improving the response of the sensors to detect a low concentration of gas. However, factors that make a large response, such as abundant or strong adsorption sites, also work as a source of noise, resulting in a trade-off between response and noise. Thus, the response alone cannot fully evaluate the performance of sensors, and the signal-to-noise-ratio (SNR) should additionally be considered to design gas sensors with optimal performance. In this regard, thin-film-type sensing materials are good candidates thanks to their moderate response and noise level. In this paper, we investigate the effects of radio frequency (RF) sputtering power for deposition of sensing materials on the SNR of resistor- and field-effect transistor (FET)-type gas sensors fabricated on the same Si wafer. In the case of resistor-type gas sensors, the deposition conditions that improve the response also worsen the noise either by increasing the scattering at the bulk or damaging the interface of the sensing material. Among resistor-type gas sensors with sensing materials deposited with different RF powers, a sensor with low noise shows the largest SNR despite its small response. However, the noise of FET-type gas sensors is not affected by changes in RF power and thus there is no trade-off between response and noise. The results reveal different noise sources depending on the deposition conditions of the sensing material, and provide design guidelines for resistor- and FET-type gas sensors considering noise for optimal performance.

On-Chip Training Spiking Neural Networks Using Approximated Backpropagation With Analog Synaptic Devices.

Hardware-based spiking neural networks (SNNs) inspired by a biological nervous system are regarded as an innovative computing system with very low power consumption and massively parallel operation. To train SNNs with supervision, we propose an efficient on-chip training scheme approximating backpropagation algorithm suitable for hardware implementation. We show that the accuracy of the proposed scheme for SNNs is close to that of conventional artificial neural networks (ANNs) by using the stochastic characteristics of neurons. In a hardware configuration, gated Schottky diodes (GSDs) are used as synaptic devices, which have a saturated current with respect to the input voltage. We design the SNN system by using the proposed on-chip training scheme with the GSDs, which can update their conductance in parallel to speed up the overall system. The performance of the on-chip training SNN system is validated through MNIST data set classification based on network size and total time step. The SNN systems achieve accuracy of 97.83% with 1 hidden layer and 98.44% with 4 hidden layers in fully connected neural networks. We then evaluate the effect of non-linearity and asymmetry of conductance response for long-term potentiation (LTP) and long-term depression (LTD) on the performance of the on-chip training SNN system. In addition, the impact of device variations on the performance of the on-chip training SNN system is evaluated.

Analysis of a Schottky Barrier MOSFET for Synaptic Device Using Hot Carrier Injection.

In this paper, we analyze the hot carrier injection (HCI) in an asymmetric dual-gate structure with a metallic source/drain. We propose a program/erase scheme where HCI occurs on the source side of the body. Owing to the large resistance of the Schottky barrier used, a large electric field is formed around the Schottky barrier. Therefore, impact ionization occurs as the gate voltage is increased and hot carriers are injected into the source side, which is less influenced by the drain voltage. We also analyze the program and erase efficiency by adjusting the Schottky barrier height or by using dopant segregation technique. We expect a small amount of current to flow and great efficiency of the program/erase operations to use as a synaptic device.

Pruning for Hardware-Based Deep Spiking Neural Networks Using Gated Schottky Diode as Synaptic Devices.

Deep learning represents state-of-the-art results in various machine learning tasks, but for applications that require real-time inference, the high computational cost of deep neural networks becomes a bottleneck for the efficiency. To overcome the high computational cost of deep neural networks, spiking neural networks (SNN) have been proposed. Herein, we propose a hardware implementation of the SNN with gated Schottky diodes as synaptic devices. In addition, we apply L1 regularization for connection pruning of the deep spiking neural networks using gated Schottky diodes as synap-tic devices. Applying L1 regularization eliminates the need for a re-training procedure because it prunes the weights based on the cost function. The compressed hardware-based SNN is energy efficient while achieving a classification accuracy of 97.85% which is comparable to 98.13% of the software deep neural networks (DNN).

A Simulation Study on Reducing the Grain Boundary Position Dependency in Tunneling Thin-Film Transistors Using a Wide Tunneling Area.

In this paper, we confirmed the effect of the grain boundary position dependency on short channel poly-Si Tunneling TFTs using technology computer aided design (TCAD) simulation. The simulation results show that the grain boundary (GB) in the channel affects the tunneling barrier and thus, produces variations in the electrical characteristics of the device such as the Vth and off-current. In the case of tunneling TFTs, the characteristics of the entire device are determined by the band to band tunneling (BTBT) currents occurring in very limited regions. In this study, we proposed that a TFT device requires a wider BTBT region because this limited region worsens the variations in the electrical characteristics of the TFT device. Two additional methods were proposed, one using vertical BTBT over a wide area through an additional poly-Si layer deposition and one widening the BTBT area through tilting implantation without an additional deposition process. The simulation results show that the variation of Vth is reduced to 10% through the extension of the BTBT area.

Synaptic Characteristics of Amorphous Boron Nitride-Based Memristors on a Highly Doped Silicon Substrate for Neuromorphic Engineering.

In this study, the resistive switching and synaptic properties of a complementary metal-oxide semiconductor-compatible Ti/a-BN/Si device are investigated for neuromorphic systems. A gradual change in resistance is observed in a positive SET operation in which Ti diffusion is involved in the conducting path. This operation is extremely suitable for synaptic devices in hardware-based neuromorphic systems. The isosurface charge density plots and experimental results confirm that boron vacancies can help generate a conducting path, whereas the conducting path generated by a Ti cation from interdiffusion forms is limited. A negative SET operation causes a considerable decrease in the formation energy of only boron vacancies, thereby increasing the conductivity in the low-resistance state, which may be related to RESET failure and poor endurance. The pulse transient characteristics, potentiation and depression characteristics, and good retention property of eight multilevel cells also indicate that the positive SET operation is more suitable for a synaptic device owing to the gradual modulation of conductance. Moreover, pattern recognition accuracy is examined by considering the conductance values of the measured data in the Ti/a-BN/Si device as the synaptic part of a neural network. The linear and symmetric synaptic weight update in a positive SET operation with an incremental voltage pulse scheme ensures higher pattern recognition accuracy.