Two-Dimensional Tunneling Memtransistor with Thin-Film Heterostructure for Low-Power Logic-in-Memory Complementary Metal-Oxide Semiconductor.

With the demand for high-performance and miniaturized semiconductor devices continuously rising, the development of innovative tunneling transistors via efficient stacking methods using two-dimensional (2D) building blocks has paramount importance in the electronic industry. Hence, 2D semiconductors with atomically thin geometries hold significant promise for advancements in electronics. In this study, we introduced tunneling memtransistors with a thin-film heterostructure composed of 2D semiconducting MoS2 and WSe2. Devices with the dual function of tuning and memory operation were realized by the gate-regulated modulation of the barrier height at the heterojunction and manipulation of intrinsic defects within the exfoliated nanoflakes using solution processes. Further, our investigation revealed extensive edge defects and four distinct defect types, namely monoselenium vacancies, diselenium vacancies, tungsten vacancies, and tungsten adatoms, in the interior of electrochemically exfoliated WSe2 nanoflakes. Additionally, we constructed complementary metal-oxide semiconductor-based logic-in-memory devices with a small static power in the range of picowatts using the developed tunneling memtransistors, demonstrating a promising approach for next-generation low-power nanoelectronics.

Selenium-alloyed tellurium oxide for amorphous p-channel transistors.

Compared to polycrystalline semiconductors, amorphous semiconductors offer inherent cost-effective, simple and uniform manufacturing. Traditional amorphous hydrogenated Si falls short in electrical properties, necessitating the exploration of new materials. The creation of high-mobility amorphous n-type metal oxides, such as a-InGaZnO (ref. 1), and their integration into thin-film transistors (TFTs) have propelled advancements in modern large-area electronics and new-generation displays2-8. However, finding comparable p-type counterparts poses notable challenges, impeding the progress of complementary metal-oxide-semiconductor technology and integrated circuits9-11. Here we introduce a pioneering design strategy for amorphous p-type semiconductors, incorporating high-mobility tellurium within an amorphous tellurium suboxide matrix, and demonstrate its use in high-performance, stable p-channel TFTs and complementary circuits. Theoretical analysis unveils a delocalized valence band from tellurium 5p bands with shallow acceptor states, enabling excess hole doping and transport. Selenium alloying suppresses hole concentrations and facilitates the p-orbital connectivity, realizing high-performance p-channel TFTs with an average field-effect hole mobility of around 15 cm2 V-1 s-1 and on/off current ratios of 106-107, along with wafer-scale uniformity and long-term stabilities under bias stress and ambient ageing. This study represents a crucial stride towards establishing commercially viable amorphous p-channel TFT technology and complementary electronics in a low-cost and industry-compatible manner.

High-Performance Solution-Processed 2D P-Type WSe2 Transistors and Circuits through Molecular Doping.

Semiconducting ink based on 2D single-crystal flakes with dangling-bond-free surfaces enables the implementation of high-performance devices on form-free substrates by cost-effective and scalable printing processes. However, the lack of solution-processed p-type 2D semiconducting inks with high mobility is an obstacle to the development of complementary integrated circuits. Here, a versatile strategy of doping with Br2 is reported to enhance the hole mobility by orders of magnitude for p-type transistors with 2D layered materials. Br2 -doped WSe2 transistors show a field-effect hole mobility of more than 27 cm2  V-1  s-1 , and a high on/off current ratio of ≈107 , and exhibits excellent operational stability during the on-off switching, cycling, and bias stressing testing. Moreover, complementary inverters composed of patterned p-type WSe2 and n-type MoS2 layered films are demonstrated with an ultra-high gain of 1280 under a driving voltage (VDD ) of 7 V. This work unveils the high potential of solution-processed 2D semiconductors with low-temperature processability for flexible devices and monolithic circuitry.

Evaporated nanometer chalcogenide films for scalable high-performance complementary electronics.

The exploration of stable and high-mobility semiconductors that can be grown over a large area using cost-effective methods continues to attract the interest of the electronics community. However, many mainstream candidates are challenged by scarce and expensive components, manufacturing costs, low stability, and limitations of large-area growth. Herein, we report wafer-scale ultrathin (metal) chalcogenide semiconductors for high-performance complementary electronics using standard room temperature thermal evaporation. The n-type bismuth sulfide delivers an in-situ transition from a conductor to a high-mobility semiconductor after mild post-annealing with self-assembly phase conversion, achieving thin-film transistors with mobilities of over 10 cm2 V-1 s-1, on/off current ratios exceeding 108, and high stability. Complementary inverters are constructed in combination with p-channel tellurium device with hole mobilities of over 50 cm2 V-1 s-1, delivering remarkable voltage transfer characteristics with a high gain of 200. This work has laid the foundation for depositing scalable electronics in a simple and cost-effective manner, which is compatible with monolithic integration with commercial products such as organic light-emitting diodes.

Sn-Based Perovskite Halides for Electronic Devices.

Because of its less toxicity and electronic structure analogous to that of lead, tin halide perovskite (THP) is currently one of the most favorable candidates as an active layer for optoelectronic and electric devices such as solar cells, photodiodes, and field-effect transistors (FETs). Promising photovoltaics and FETs performances have been recently demonstrated because of their desirable electrical and optical properties. Nevertheless, THP's easy oxidation from Sn2+ to Sn4+ , easy formation of tin vacancy, uncontrollable film morphology and crystallinity, and interface instability severely impede its widespread application. This review paper aims to provide a basic understanding of THP as a semiconductor by highlighting the physical structure, energy band structure, electrical properties, and doping mechanisms. Additionally, the key chemical instability issues of THPs are discussed, which are identified as the potential bottleneck for further device development. Based on the understanding of the THPs properties, the key recent progress of THP-based solar cells and FETs is briefly discussed. To conclude, current challenges and perspective opportunities are highlighted.

Photonic nanostructures mimicking floral epidermis for perovskite solar cells.

Here, we report photonic nanostructures replicated from the adaxial epidermis of flower petals onto light-polymerized coatings using low-cost nanoimprint lithography at ambient temperature. These multifunctional nanocoatings are applied to confer enhanced light trapping, water repellence, and UV light and environmental moisture protection features in perovskite solar cells. The former feature helps attain a maximum power conversion efficiency of 24.61% (21.01% for the reference cell) without any additional device optimization. Added to these merits, the nanocoatings also enable stable operation under AM 1.5G and UV light continuous illumination or in real-world conditions. Our engineering approach provides a simple way to produce multifunctional nanocoatings optimized by nature's wisdom.

High-performance hysteresis-free perovskite transistors through anion engineering.

Despite the impressive development of metal halide perovskites in diverse optoelectronics, progress on high-performance transistors employing state-of-the-art perovskite channels has been limited due to ion migration and large organic spacer isolation. Herein, we report high-performance hysteresis-free p-channel perovskite thin-film transistors (TFTs) based on methylammonium tin iodide (MASnI3) and rationalise the effects of halide (I/Br/Cl) anion engineering on film quality improvement and tin/iodine vacancy suppression, realising high hole mobilities of 20 cm2 V-1 s-1, current on/off ratios exceeding 107, and threshold voltages of 0 V along with high operational stabilities and reproducibilities. We reveal ion migration has a negligible contribution to the hysteresis of Sn-based perovskite TFTs; instead, minority carrier trapping is the primary cause. Finally, we integrate the perovskite TFTs with commercialised n-channel indium gallium zinc oxide TFTs on a single chip to construct high-gain complementary inverters, facilitating the development of halide perovskite semiconductors for printable electronics and circuits.

Sodium Incorporation for Enhanced Performance of Two-Dimensional Sn-Based Perovskite Transistors.

Two-dimensional metal halide perovskites (2D MHPs) are promising candidates for transistor channel materials because of their high mobility in the lateral direction; however, Sn-based 2D MHPs exhibit poor film quality and oxidation stability. Here, we report a simple method to improve the performance and stability of 2D MHP transistors by incorporating sodium iodide (NaI) additives. By adding 1 vol % NaI (Na1), the transistors with phenethylammonium tin iodide (PEA2SnI4) exhibited reduced dual-sweep hysteresis, robust bias stability, and larger hole mobility (2.13 cm2 V-1 s-1) than that of a pristine device (0.39 cm2 V-1 s-1). Improvements in the film quality, such as increased grain size, crystallinity, and better film coverage, were observed in the PEA2SnI4:NaI film. In addition, NaI effectively passivated the iodine vacancies at the grain boundaries, thereby suppressing the defects.