RESUMEN
We demonstrate the growth of 3C-SiC with reduced planar defects on a micro-scale compliant substrate. Heteroepitaxial growth of 3C-SiC on trenches with a width and separation of 2 µm, etched into a Si(001) substrate, is found to suppress defect propagation through the epilayer. Stacking faults and other planar defects are channeled away from the center of the patterned structures, which are rounded through the use of H2 annealing at 1100 °C. Void formation between the columns of 3C-SiC growth acts as a termination point for defects, and coalescence of these columns into a continuous epilayer is promoted through the addition of HCl in the growth phase. The process of fabricating these compliant substrates utilizes standard processing techniques found within the semiconductor industry and is independent of the substrate orientation and offcut.
