RESUMEN
A synergistic approach that incorporates first-principles atomistic modeling with numerical device simulations is used to systematically evaluate the role of heterointerfaces within metal-chalcogenide-based photovoltaic technologies. Two interfaces involving either a tellurium back contact or aluminum back electrode combined with a cadmium telluride absorber layer within cadmium-telluride-based thin-film solar cells are investigated on an atomic scale to determine the mechanisms contributing to variations in device performance. Electronic structures and predicted charge transport behavior with respect to cadmium and tellurium termination of the absorber layer are studied along the polar oriented CdTe{111} facets. The computational methodology reveals a noticeable contrast between the Schottky barrier forming Al/CdTe interface versus the Type I Te/CdTe heterojunction. Greater band bending features are exhibited by the cadmium termination as opposed to the tellurium termination for each interface case. Subsequent device modeling suggests that 3.6% higher photovoltaic conversion efficiency is achievable for the cadmium termination relative to the tellurium termination of the Te/CdTe interface. Based strictly on an idealistic representation, both interface models show the importance of atomic-scale interfacial properties for cadmium telluride solar cell device performance with their bulk properties being validated in comparison to published experimental data. The synergistic approach offers a suitable method to analyze solar cell interfaces through a predictive computational framework for the engineering and optimization of metal-chalcogenide-based thin-film photovoltaic technologies.
RESUMEN
Developments in photovoltaic device architectures are necessary to make solar energy a cost-effective and reliable source of renewable energy amidst growing global energy demands and climate change. Thin film CdTe technology has demonstrated cost-competitiveness and increasing efficiencies due partially to rapid fabrication times, minimal material usage, and introduction of a CdSeTe alloy into a ~3 µm absorber layer. This work presents the close-space sublimation fabrication of thin, 1.5 µm CdSeTe/CdTe bilayer devices using an automated in-line vacuum deposition system. The thin bilayer structure and fabrication technique minimize deposition time, increase device efficiency, and facilitate future thin absorber-based device architecture development. Three fabrication parameters appear to be the most impactful for optimizing thin CdSeTe/CdTe absorber devices: substrate preheat temperature, CdSeTe:CdTe thickness ratio, and CdCl2 passivation. For proper sublimation of the CdSeTe, the substrate temperature prior to deposition must be ~540 °C (higher than that for CdTe) as controlled by dwell time in a preheat source. Variation in the CdSeTe:CdTe thickness ratio reveals a strong dependence of device performance on this ratio. The optimal absorber thicknesses are 0.5 µm CdSeTe/1.0 µm CdTe, and non-optimized thickness ratios reduce efficiency through back-barrier effects. Thin absorbers are sensitive to CdCl2 passivation variation; a much less aggressive CdCl2 treatment (compared to thicker absorbers) regarding both temperature and time yields optimal device performance. With optimized fabrication conditions, CdSeTe/CdTe increases device short-circuit current density and photoluminescence intensity compared to single-absorber CdTe. Additionally, an in-line close-space sublimation vacuum deposition system offers material and time reduction, scalability, and attainability of future ultra-thin absorber architectures.
