RESUMEN
The semiconductor industry is transitioning to the 'More Moore' era, driven by the adoption of three-dimensional (3D) integration schemes surpassing the limitations of traditional two-dimensional scaling. Although innovative packaging solutions have made 3D integrated circuits (ICs) commercially viable, the inclusion of through-silicon vias and microbumps brings about increased area overhead and introduces parasitic capacitances that limit overall performance. Monolithic 3D integration (M3D) is regarded as the future of 3D ICs, yet its application faces hurdles in silicon ICs due to restricted thermal processing budgets in upper tiers, which can degrade device performance. To overcome these limitations, emerging materials like carbon nanotubes and two-dimensional semiconductors have been integrated into the back end of silicon ICs. Here we report the M3D integration of complementary WSe2 FETs, in which n-type FETs are placed in tier 1 and p-type FETs are placed in tier 2. In particular, we achieve dense and scaled integration through 300 nm vias with a pitch of <1 µm, connecting more than 300 devices in tiers 1 and 2. Moreover, we have effectively implemented vertically integrated logic gates, encompassing inverters, NAND gates and NOR gates. Our demonstration highlights the two-dimensional materials' role in advancing M3D integration in complementary metal-oxide-semiconductor circuits.
RESUMEN
Atomically thin semiconductors are of interest for future electronics applications, and much attention has been given to monolayer (1L) sulfides, such as MoS2, grown by chemical vapor deposition (CVD). However, reports on the electrical properties of CVD-grown selenides, and MoSe2 in particular, are scarce. Here, we compare the electrical properties of 1L and bilayer (2L) MoSe2 grown by CVD and capped by sub-stoichiometric AlOx. The 2L channels exhibit â¼20× lower contact resistance (RC) and â¼30× larger current density compared with 1L channels. RC is further reduced by >5× with AlOx capping, which enables improved transistor current density. Overall, 2L AlOx-capped MoSe2 transistors (with â¼500 nm channel length) achieve improved current density (â¼65 µA/µm at VDS = 4 V), a good Ion/Ioff ratio of >106, and an RC of â¼60 kΩ·µm. The weaker performance of 1L devices is due to their sensitivity to processing and ambient. Our results suggest that 2L (or few layers) is preferable to 1L for improved electronic properties in applications that do not require a direct band gap, which is a key finding for future two-dimensional electronics.
RESUMEN
The use of multilayer semiconductor heterojunction structures has shown promise in infrared detector applications. Several heterostructures with innovative compositional and architectural designs have been displayed on emerging infrared technologies. In this review, we aim to illustrate the principles of heterostructure detectors for infrared detection and explore the recent progress on the development of detectors with the split-off band and threshold wavelength extension mechanism. This review article includes an understanding of the compositional and the architectural design of split-off band detectors and to prepare a database of their performances for the wavelength extension mechanism. Preparing a unique database of the compositional or architectural design of structures, their performance, and penetrating the basics of infrared detection mechanisms can lead to significant improvements in the quality of research. The brief outlook of the fundamentals of the infrared detection technique with its appropriateness and limitations for better performance is also provided. The results of the long-term study presented in this review article would be of considerable assistance to those who are focused on the heterostructure infrared detector development.
