NeuroBus - Architecture for an Ultra-Flexible Neural Interface.

This article presents the system architecture for an implant concept called NeuroBus. Tiny distributed direct digitizing neural recorder ASICs on an ultra-flexible polyimide substrate are connected in a bus-like structure, allowing short connections between electrode and recording front-end with low wiring effort and high customizability. The small size (344 µm × 294 µm) of the ASICs and the ultraflexible substrate allow a low bending stiffness, enabling the implant to adapt to the curvature of the brain and achieving high structural biocompatibility. We introduce the architecture, the integrated building blocks, and the post-CMOS processes required to realize a NeuroBus, and we characterize the prototyped direct digitizing neural recorder front-end as well as polyimide-based ECoG brain interface. A rodent animal model is further used to validate the joint capability of the recording front-end and thin-film electrode array.

Highly conformable chip-in-foil implants for neural applications.

Demands for neural interfaces around functionality, high spatial resolution, and longevity have recently increased. These requirements can be met with sophisticated silicon-based integrated circuits. Embedding miniaturized dice in flexible polymer substrates significantly improves their adaptation to the mechanical environment in the body, thus improving the systems' structural biocompatibility and ability to cover larger areas of the brain. This work addresses the main challenges in developing a hybrid chip-in-foil neural implant. Assessments considered (1) the mechanical compliance to the recipient tissue that allows a long-term application and (2) the suitable design that allows the implant's scaling and modular adaptation of chip arrangement. Finite element model studies were performed to identify design rules regarding die geometry, interconnect routing, and positions for contact pads on dice. Providing edge fillets in the die base shape proved an effective measure to improve die-substrate integrity and increase the area available for contact pads. Furthermore, routing of interconnects in the immediate vicinity of die corners should be avoided, as the substrate in these areas is prone to mechanical stress concentration. Contact pads on dice should be placed with a clearance from the die rim to avoid delamination when the implant conforms to a curvilinear body. A microfabrication process was developed to transfer, align, and electrically interconnect multiple dice into conformable polyimide-based substrates. The process enabled arbitrary die shape and size over independent target positions on the conformable substrate based on the die position on the fabrication wafer.

A Direct Digitizing Chopped Neural Recorder Using a Body-Induced Offset Based DC Servo Loop.

This article presents a direct digitizing neural recorder that uses a body-induced offset based DC servo loop to cancel electrode offset (EDO) on-chip. The bulk of the input pair is used to create an offset, counteracting the EDO. The architecture does not require AC coupling capacitors which enables the use of chopping without impedance boosting while maintaining a large input impedance of 238 M Ω over the whole 10 kHz bandwidth. Implemented in a 180 nm HV-CMOS process, the prototype occupies a silicon area of only 0.02 mm2 while consuming 12.8 µW and achieving 1.82 µV[Formula: see text] of input-referred noise in the local field potential (LFP) band and a NEF of 5.75.

A Chopped Neural Front-End Featuring Input Impedance Boosting With Suppressed Offset-Induced Charge Transfer.

Modern neuromodulation systems typically provide a large number of recording and stimulation channels, which reduces the available power and area budget per channel. To maintain the necessary input-referred noise performance despite growingly rigorous area constraints, chopped neural front-ends are often the modality of choice, as chopper-stabilization allows to simultaneously improve (1/f) noise and area consumption. The resulting issue of a drastically reduced input impedance has been addressed in prior art by impedance boosters based on voltage buffers at the input. These buffers precharge the large input capacitors, reduce the charge drawn from the electrodes and effectively boost the input impedance. Offset on these buffers directly translates into charge-transfer to the electrodes, which can accelerate electrode aging. To tackle this issue, a voltage buffer with ultra-low time-averaged offset is proposed, which cancels offset by periodic reconfiguration, thereby minimizing unintended charge transfer. This article explains the background and circuit design in detail and presents measurement results of a prototype implemented in a 180 nm HV CMOS process. The measurements confirm that signal-independent, buffer offset induced charge transfer occurs and can be mitigated by the presented buffer reconfiguration without adversely affecting the operation of the input impedance booster. The presented neural recorder front-end achieves state of the art performance with an area consumption of 0.036 mm2, an input referred noise of [Formula: see text] (1 to 200 Hz) and [Formula: see text] (0.2 to 10 kHz), power consumption of 13.7 µW from 1.8 V supply, as well as CMRR and PSRR ≥ 83 dB at 50 Hz.