RESUMEN
When thickness-dependent carrier mobility is coupled with Thomas-Fermi screening and interlayer resistance effects in two-dimensional (2D) multilayer materials, a conducting channel migrates from the bottom surface to the top surface under electrostatic bias conditions. However, various factors including (i) insufficient carrier density, (ii) atomically thin material thickness, and (iii) numerous oxide traps/defects considerably limit our deep understanding of the carrier transport mechanism in 2D multilayer materials. Herein, we report the restricted conducting channel migration in 2D multilayer ReS2 after a constant voltage stress of gate dielectrics is applied. At a given gate bias condition, a gradual increase in the drain bias enables a sensitive change in the interlayer resistance of ReS2, leading to a modification of the shape of the transconductance curves, and consequently, demonstrates the conducting channel migration along the thickness of ReS2 before the stress. Meanwhile, this distinct conduction feature disappears after stress, indicating the formation of additional oxide trap sites inside the gate dielectrics that degrade the carrier mobility and eventually restrict the channel migration. Our theoretical and experimental study based on the resistor network model and Thomas-Fermi charge screening theory provides further insights into the origins of channel migration and restriction in 2D multilayer devices.
RESUMEN
Through time-dependent defect spectroscopy and low-frequency noise measurements, we investigate and characterize the differences of carrier trapping processes occurred by different interfaces (top/sidewall) of the gate-all-around silicon nanosheet field-effect transistor (GAA SiNS FET). In a GAA SiNS FET fabricated by the top-down process, the traps at the sidewall interface significantly affect the device performance as the width decreases. Compare to expectations, as the width of the device decreases, the subthreshold swing (SS) increases from 120 to 230 mV/dec, resulting in less gate controllability. In narrow-width devices, the effect of traps located at the sidewall interface is significantly dominant, and the 1/f 2 noise, also known as generation-recombination (G-R) noise, is clearly appeared with an increased time constant (τ i ). In addition, the probability density distributions for the normalized current fluctuations (ΔI D) show only one Gaussian in wide-width devices, whereas they are separated into four Gaussians with increased in narrow-width devices. Therefore, fitting is performed through the carrier number fluctuation-correlated with mobility fluctuations model that separately considered the effects of sidewall. In narrow-width GAA SiNS FETs, consequently, the extracted interface trap densities (N T ) distribution becomes more dominant, and the scattering parameter ([Formula: see text]) distribution increases by more than double.
