Large-scale sub-5-nm vertical transistors by van der Waals integration.

Vertical field effect transistor (VFET), in which the semiconductor is sandwiched between source/drain electrodes and the channel length is simply determined by the semiconductor thickness, has demonstrated promising potential for short channel devices. However, despite extensive efforts over the past decade, scalable methods to fabricate ultra-short channel VFETs remain challenging. Here, we demonstrate a layer-by-layer transfer process of large-scale indium gallium zinc oxide (IGZO) semiconductor arrays and metal electrodes, and realize large-scale VFETs with ultra-short channel length and high device performance. Within this process, the oxide semiconductor could be pre-deposited on a sacrificial wafer, and then physically released and sandwiched between metals, maintaining the intrinsic properties of ultra-scaled vertical channel. Based on this lamination process, we realize 2 inch-scale VFETs with channel length down to 4 nm, on-current over 800 A/cm2, and highest on-off ratio up to 2 × 105, which is over two orders of magnitude higher compared to control samples without laminating process. Our study not only represents the optimization of VFETs performance and scalability at the same time, but also offers a method of transfer large-scale oxide arrays, providing interesting implication for ultra-thin vertical devices.

High-density vertical sidewall MoS2 transistors through T-shape vertical lamination.

Vertical transistors, in which the source and drain are aligned vertically and the current flow is normal to the wafer surface, have attracted considerable attention recently. However, the realization of high-density vertical transistors is challenging, and could be largely attributed to the incompatibility between vertical structures and conventional lateral fabrication processes. Here we report a T-shape lamination approach for realizing high-density vertical sidewall transistors, where lateral transistors could be pre-fabricated on planar substrates first and then laminated onto vertical substrates using T-shape stamps, hence overcoming the incompatibility between planar processes and vertical structures. Based on this technique, we vertically stacked 60 MoS2 transistors within a small vertical footprint, corresponding to a device density over 108 cm-2. Furthermore, we demonstrate two approaches for scalable fabrication of vertical sidewall transistor arrays, including simultaneous lamination onto multiple vertical substrates, as well as on the same vertical substrate using multi-cycle layer-by-layer laminations.

Monolithic three-dimensional tier-by-tier integration via van der Waals lamination.

Two-dimensional (2D) semiconductors have shown great potential for monolithic three-dimensional (M3D) integration due to their dangling-bonds-free surface and the ability to integrate to various substrates without the conventional constraint of lattice matching1-10. However, with atomically thin body thickness, 2D semiconductors are not compatible with various high-energy processes in microelectronics11-13, where the M3D integration of multiple 2D circuit tiers is challenging. Here we report an alternative low-temperature M3D integration approach by van der Waals (vdW) lamination of entire prefabricated circuit tiers, where the processing temperature is controlled to 120 °C. By further repeating the vdW lamination process tier by tier, an M3D integrated system is achieved with 10 circuit tiers in the vertical direction, overcoming previous thermal budget limitations. Detailed electrical characterization demonstrates the bottom 2D transistor is not impacted after repetitively laminating vdW circuit tiers on top. Furthermore, by vertically connecting devices within different tiers through vdW inter-tier vias, various logic and heterogeneous structures are realized with desired system functions. Our demonstration provides a low-temperature route towards fabricating M3D circuits with increased numbers of tiers.

Ultrashort vertical-channel MoS2 transistor using a self-aligned contact.

Two-dimensional (2D) semiconductors hold great promises for ultra-scaled transistors. In particular, the gate length of MoS2 transistor has been scaled to 1 nm and 0.3 nm using single wall carbon nanotube and graphene, respectively. However, simultaneously scaling the channel length of these short-gate transistor is still challenging, and could be largely attributed to the processing difficulties to precisely align source-drain contact with gate electrode. Here, we report a self-alignment process for realizing ultra-scaled 2D transistors. By mechanically folding a graphene/BN/MoS2 heterostructure, source-drain metals could be precisely aligned around the folded edge, and the channel length is only dictated by heterostructure thickness. Together, we could realize sub-1 nm gate length and sub-50 nm channel length for vertical MoS2 transistor simultaneously. The self-aligned device exhibits on-off ratio over 105 and on-state current of 250 µA/µm at 4 V bias, which is over 40 times higher compared to control sample without self-alignment process.

Ag-Assisted Dry Exfoliation of Large-Scale and Continuous 2D Monolayers.

Two-dimensional (2D) semiconductors have generated considerable attention for high-performance electronics and optoelectronics. However, to date, it is still challenging to mechanically exfoliate large-area and continuous monolayers while retaining their intrinsic properties. Here, we report a simple dry exfoliation approach to produce large-scale and continuous 2D monolayers by using a Ag film as the peeling tape. Importantly, the conducting Ag layer could be converted into AgOx nanoparticles at low annealing temperature, directly decoupling the conducting Ag with the underlayer 2D monolayers without involving any solution or etching process. Electrical characterization of the monolayer MoS2 transistor shows a decent carrier mobility of 42 cm2 V-1 s-1 and on-state current of 142 µA/µm. Finally, a plasmonic enhancement photodetector could be simultaneously realized due to the direct formation of Ag nanoparticles arrays on MoS2 monolayers, without complex approaches for nanoparticle synthesis and integration processes, demonstrating photoresponsivity and detectivity of 6.3 × 105 A/W and 2.3 × 1013 Jones, respectively.

Realizing On/Off Ratios over 104 for Sub-2 nm Vertical Transistors.

Vertical transistors hold promise for the development of ultrascaled transistors. However, their on/off ratios are limited by a strong source-drain tunneling current in the off state, particularly for vertical devices with a sub-5 nm channel length. Here, we report an approach for suppressing the off-state tunneling current by designing the barrier height via a van der Waals metal contact. Via lamination of the Pt electrode on a MoS2 vertical transistor, a high Schottky barrier is observed due to their large work function difference, thus suppressing direct tunneling currents. Meanwhile, this "low-energy" lamination process ensures an optimized metal/MoS2 interface with minimized interface states and defects. Together, the highest on/off ratios of 5 × 105 and 104 are realized in vertical transistors with 5 and 2 nm channel lengths, respectively. Our work not only pushes the on/off ratio limit of vertical transistors but also provides a general rule for reducing short-channel effects in ultrascaled devices.

Mobility Enhancement of Strained MoS2 Transistor on Flat Substrate.

Strain engineering has been proposed as a promising method to boost the carrier mobility of two-dimensional (2D) semiconductors. However, state-of-the-art straining approaches are largely based on putting 2D semiconductors on flexible substrates or rough substrate with nanostructures (e.g., nanoparticles, nanorods, ripples), where the observed mobility change is not only dependent on channel strain but could be impacted by the change of dielectric environment as well as rough interface scattering. Therefore, it remains an open question whether the pure lattice strain could improve the carrier mobilities of 2D semiconductors, limiting the achievement of high-performance 2D transistors. Here, we report a strain engineering approach to fabricate highly strained MoS2 transistors on a flat substrate. By mechanically laminating a prefabricated MoS2 transistor onto a custom-designed trench structure on flat substrate, well-controlled strain can be uniformly generated across the 2D channel. In the meantime, the substrate and the back-gate dielectric layer remain flat without any roughness-induced scattering effect or variation of the dielectric environment. Based on this technique, we demonstrate the MoS2 electron mobility could be enhanced by tension strain and decreased by compression strain, consistent with theoretical predictions. The highest mobility enhancement is 152% for monolayer MoS2 and 64% for bilayer MoS2 transistors, comparable to that of a silicon device. Our method not only provides a compatible approach to uniformly strain the layered semiconductors on flat and solid substrate but also demonstrates an effective method to boost the carrier mobilities of 2D transistors.

Wafer-scale high-κ dielectrics for two-dimensional circuits via van der Waals integration.

The practical application of two-dimensional (2D) semiconductors for high-performance electronics requires the integration with large-scale and high-quality dielectrics-which however have been challenging to deposit to date, owing to their dangling-bonds-free surface. Here, we report a dry dielectric integration strategy that enables the transfer of wafer-scale and high-κ dielectrics on top of 2D semiconductors. By utilizing an ultra-thin buffer layer, sub-3 nm thin Al2O3 or HfO2 dielectrics could be pre-deposited and then mechanically dry-transferred on top of MoS2 monolayers. The transferred ultra-thin dielectric film could retain wafer-scale flatness and uniformity without any cracks, demonstrating a capacitance up to 2.8 µF/cm2, equivalent oxide thickness down to 1.2 nm, and leakage currents of ~10-7 A/cm2. The fabricated top-gate MoS2 transistors showed intrinsic properties without doping effects, exhibiting on-off ratios of ~107, subthreshold swing down to 68 mV/dec, and lowest interface states of 7.6×109 cm-2 eV-1. We also show that the scalable top-gate arrays can be used to construct functional logic gates. Our study provides a feasible route towards the vdW integration of high-κ dielectric films using an industry-compatible ALD process with well-controlled thickness, uniformity and scalability.

Wafer-scale and universal van der Waals metal semiconductor contact.

Van der Waals (vdW) metallic contacts have been demonstrated as a promising approach to reduce the contact resistance and minimize the Fermi level pinning at the interface of two-dimensional (2D) semiconductors. However, only a limited number of metals can be mechanically peeled and laminated to fabricate vdW contacts, and the required manual transfer process is not scalable. Here, we report a wafer-scale and universal vdW metal integration strategy readily applicable to a wide range of metals and semiconductors. By utilizing a thermally decomposable polymer as the buffer layer, different metals were directly deposited without damaging the underlying 2D semiconductor channels. The polymer buffer could be dry-removed through thermal annealing. With this technique, various metals could be vdW integrated as the contact of 2D transistors, including Ag, Al, Ti, Cr, Ni, Cu, Co, Au, Pd. Finally, we demonstrate that this vdW integration strategy can be extended to bulk semiconductors with reduced Fermi level pinning effect.

Thickness-Dependent Topological Hall Effect in 2D Cr5 Si3 Nanosheets with Noncollinear Magnetic Phase.

Antiferromagnets with noncollinear spin order are expected to exhibit unconventional electromagnetic response, such as spin Hall effects, chiral abnormal, quantum Hall effect, and topological Hall effect. Here, 2D thickness-controlled and high-quality Cr5 Si3 nanosheets that are compatible with the complementary metal-oxide-semiconductor technology are synthesized by chemical vapor deposition method. The angular dependence of electromagnetic transport properties of Cr5 Si3 nanosheets is investigated using a physical property measurement system, and an obvious topological Hall effect (THE) appears at a large tilted magnetic field, which results from the noncollinear magnetic structure of the Cr5 Si3 nanosheet. The Cr5 Si3 nanosheets exhibit distinct thickness-dependent perpendicular magnetic anisotropy (PMA), and the THE only emerges in the specific thickness range with moderate PMA. This work provides opportunities for exploring fundamental spin-related physical mechanisms of noncollinear antiferromagnet in ultrathin limit.

Realization of Ultra-Scaled MoS2 Vertical Diodes via Double-Side Electrodes Lamination.

Schottky diode is the fundamental building blocks for modern electronics and optoelectronics. Reducing the semiconductor layer thickness could shrink the vertical size of a Schottky diode, improving its speed and integration density. Here, we demonstrate a new approach to fabricate a Schottky diode with ultrashort physical length approaching atomic limit. By mechanically laminating prefabricated metal electrodes on both-sides of two-dimensional MoS2, the intrinsic metal-semiconductor interfaces can be well retained. As a result, we demonstrate the thinnest Schottky diode with a length of 2.6 nm and decent rectification behavior. Furthermore, with a diode length smaller than the semiconductor depletion length, the carrier transport mechanisms are investigated and explained by thickness-dependent and temperature-dependent electrical measurements. Our study not only pushes the scaling limit of a Schottky diode but also provides a general double-sided electrodes integration approach for other ultrathin vertical devices.

Strain-Plasmonic Coupled Broadband Photodetector Based on Monolayer MoS2.

2D Semiconductors are promising in the development of next-generation photodetectors. However, the performances of 2D photodetectors are largely limited by their poor light absorption (due to ultrathin thickness) and small detection range (due to large bandgap). To overcome the limitations, a strain-plasmonic coupled 2D photodetector is designed by mechanically integrating monolayer MoS2 on top of prefabricated Au nanoparticle arrays. Within this structure, the large biaxial tensile strain can greatly reduce the MoS2 bandgap for broadband photodetection, and at the same time, the nanoparticles can significantly enhance the light intensity around MoS2 with much improved light absorption. Together, the strain-plasmonic coupled photodetector can broaden the detection range by 60 nm and increase the signal-to-noise ratio by 650%, representing the ultimate optimization of detection range and detection intensity at the same time. The strain-plasmonic coupling effect is further systematically characterized and confirmed by using Raman and photoluminescence spectrophotometry. Furthermore, the existence of built-in potential and photo-switching behavior is demonstrated between the strained and unstrained region, constructing a self-powered homojunction photodetector. This approach provides a simple strategy to couple strain effect and plasmonic effect, which can provide a new strategy for designing high-performance and broadband 2D optoelectronic devices.

High-Resolution Van der Waals Stencil Lithography for 2D Transistors.

2D semiconductors have attracted tremendous attention as an atomically thin channel for transistors with superior immunity to short-channel effects. However, with atomic thin structure, the delicate 2D lattice is not fully compatible with conventional lithography processes that typically involve high-energy photon/electron radiation and unavoidable polymer residues, posing a key limitation for high performance 2D transistors. Here, a novel van der Waals (vdW) stencil lithography technique based on dry mask lamination process is developed. By pre-fabricating polymethyl methacrylate (PMMA) resist with designed patterns, the whole PMMA mask layers could be mechanically released from the sacrifice wafer and physically laminated on top of various 2D semiconductors. The vdW stencil lithography ensures pristine 2D surface without any high-energy electron/photon radiation, polymer residues, or chemical doping effects in conventional lithography process; and the soft nature of PMMA enables intimate contact between the mask and the 2D materials without physical gap, leading to ultra-high resolution down to 60 nm. Together, by applying vdW stencil lithography for 2D semiconductors, high performance transistors are demonstrated. Our method not only demonstrates improved 2D transistor performance without lithography induced damages, but also provides a new vdW stencil lithography technique for 2D materials with high resolution.

Reconfigurable electronics by disassembling and reassembling van der Waals heterostructures.

Van der Waals heterostructures (vdWHs) have attracted tremendous interest owing to the ability to assemble diverse building blocks without the constraints of lattice matching and processing compatibility. However, once assembled, the fabricated vdWHs can hardly be separated into individual building blocks for further manipulation, mainly due to technical difficulties in the disassembling process. Here, we show a method to disassemble the as-fabricated vdWHs into individual building blocks, which can be further reassembled into new vdWHs with different device functionalities. With this technique, we demonstrate reconfigurable transistors from n-type to p-type and back-gate to dual-gate structures through re-stacking. Furthermore, reconfigurable device behaviors from floating gate memory to Schottky diode and reconfigurable anisotropic Raman behaviors have been obtained through layer re-sequencing and re-twisting, respectively. Our results could lead to a reverse engineering concept of disassembled vdWHs electronics in parallel with state-of-the-art vdWHs electronics, offering a general method for multi-functional pluggable electronics and optoelectronics with limited material building blocks.

Rational design of Al2O3/2D perovskite heterostructure dielectric for high performance MoS2 phototransistors.

Two-dimensional (2D) Ruddlesden-Popper perovskites are currently drawing significant attention as highly-stable photoactive materials for optoelectronic applications. However, the insulating nature of organic ammonium layers in 2D perovskites results in poor charge transport and limited performance. Here, we demonstrate that Al2O3/2D perovskite heterostructure can be utilized as photoactive dielectric for high-performance MoS2 phototransistors. The type-II band alignment in 2D perovskites facilitates effective spatial separation of photo-generated carriers, thus achieving ultrahigh photoresponsivity of >108 A/W at 457 nm and >106 A/W at 1064 nm. Meanwhile, the hysteresis loops induced by ionic migration in perovskite and charge trapping in Al2O3 can neutralize with each other, leading to low-voltage phototransistors with negligible hysteresis and improved bias stress stability. More importantly, the recombination of photo-generated carriers in 2D perovskites depends on the external biasing field. With an appropriate gate bias, the devices exhibit wavelength-dependent constant photoresponsivity of 103-108 A/W regardless of incident light intensity.

Doping-free complementary WSe2 circuit via van der Waals metal integration.

Two-dimensional (2D) semiconductors have attracted considerable attention for the development of ultra-thin body transistors. However, the polarity control of 2D transistors and the achievement of complementary logic functions remain critical challenges. Here, we report a doping-free strategy to modulate the polarity of WSe2 transistors using same contact metal but different integration methods. By applying low-energy van der Waals integration of Au electrodes, we observed robust and optimized p-type transistor behavior, which is in great contrast to the transistors fabricated on the same WSe2 flake using conventional deposited Au contacts with pronounced n-type characteristics. With the ability to switch majority carrier type and to achieve optimized contact for both electrons and holes, a doping-free logic inverter is demonstrated with higher voltage gain of 340, at the bias voltage of 5.5 V. Furthermore, the simple polarity control strategy is extended for realizing more complex logic functions such as NAND and NOR.

Efficient strain modulation of 2D materials via polymer encapsulation.

Strain engineering is a promising method to manipulate the electronic and optical properties of two-dimensional (2D) materials. However, with weak van der Waals interaction, severe slippage between 2D material and substrate could dominate the bending or stretching processes, leading to inefficiency strain transfer. To overcome this limitation, we report a simple strain engineering method by encapsulating the monolayer 2D material in the flexible PVA substrate through spin-coating approach. The strong interaction force between spin-coated PVA and 2D material ensures the mechanical strain can be effectively transferred with negligible slippage or decoupling. By applying uniaxial strain to monolayer MoS2, we observe a higher bandgap modulation up to ~300 meV and a highest modulation rate of ~136 meV/%, which is approximate two times improvement compared to previous results achieved. Moreover, this simple strategy could be well extended to other 2D materials such as WS2 or WSe2, leading to enhanced bandgap modulation.