Research on the Reliability of Advanced Packaging under Multi-Field Coupling: A Review.

With the advancement of Moore's Law reaching its limits, advanced packaging technologies represented by Flip Chip (FC), Wafer-Level Packaging (WLP), System in Package (SiP), and 3D packaging have received significant attention. While advanced packaging has made breakthroughs in achieving high performance, miniaturization, and low cost, the smaller thermal space and higher power density have created complex physical fields such as electricity, heat, and stress. The packaging interconnects responsible for electrical transmission are prone to serious reliability issues, leading to the device's failure. Therefore, conducting multi-field coupling research on the reliability of advanced packaging interconnects is necessary. The development of packaging and the characteristics of advanced packaging are reviewed. The reliability issues of advanced packaging under thermal, electrical, and electromagnetic fields are discussed, as well as the methods and current research of multi-field coupling in advanced packaging. Finally, the prospect of the multi-field coupling reliability of advanced packaging is summarized to provide references for the reliability research of advanced packaging.

Delamination of Plasticized Devices in Dynamic Service Environments.

With the continuous development of advanced packaging technology in heterogeneous semiconductor integration, the delamination failure problem in a dynamic service environment has gradually become a key factor limiting the reliability of packaging devices. In this paper, the delamination failure mechanism of polymer-based packaging devices is clarified by summarizing the relevant literature and the latest research solutions are proposed. The results show that, at the microscopic scale, thermal stress and moisture damage are still the two main mechanisms of two-phase interface failure of encapsulation devices. Additionally, the application of emerging technologies such as RDL structure modification and self-healing polymers can significantly improve the thermal stress state of encapsulation devices and enhance their moisture resistance, which can improve the anti-delamination reliability of polymer-based encapsulation devices. In addition, this paper provides theoretical support for subsequent research and optimization of polymer-based packages by summarizing the microscopic failure mechanism of delamination at the two-phase interface and introducing the latest solutions.

Study on Cavitation, Warpage Deformation, and Moisture Diffusion of Sop-8 Devices during Molding Process.

Plastic packaging has shown its advantages over ceramic packaging and metal packaging in lightweight, thin, and high-density electronic devices. In this paper, the reliability and moisture diffusion of Sop-8 (Small Out-Line Package-8) plastic packaging devices are studied, and we put forward a set of complete optimization methods. Firstly, we propose to improve the reliability of plastic packaging devices by reducing the amount of cavitation and warpage deformation. Structural and process factors were investigated in the injection molding process. An orthogonal experiment design was used to create 25 groups of simulation experiments, and Moldflow software was used to simulate the flow mode analysis. Then, the simulation results are subjected to range analysis and comprehensive weighted score analysis. Finally, different optimization methods are proposed according to different production conditions, and each optimization method can reduce cavitation or warpage by more than 9%. The moisture diffusion of the Sop-8 plastic packing devices was also investigated at the same time. It was determined that the contact surface between the lead frame and the plastic packaging material was more likely to exhibit delamination under the condition of MSL2 moisture diffusion because the humidity gradient was easily produced at the crucial points of different materials. The diffusion of moisture is related to the type of plastic packaging material and the diffusion path.

Temperature Cycle Reliability Analysis of an FBAR Filter-Bonded Ceramic Package.

On the background that the operating frequency of electronic devices tends to the radio frequency (RF) segment, a film bulk acoustic resonator (FBAR) filter is widely used in communication and military fields because of its advantages of high upper frequency, ample power capacity, small size, and low cost. However, the complex and harsh working environment puts higher requirements for packaging FBAR filters. Based on the Anand constitutive equation, the stress-strain response of the bonded ceramic package was studied by the finite element method for the FBAR filter-bonded ceramic package, and the thermal fatigue life of the device was predicted. We developed solder models with various spillage morphologies based on the random generation technique to examine the impact of spillage on device temperature reliability. The following are the primary conclusions: (1) Solder undergoes periodic deformation, stress, and strain changes throughout the cycle. (2) The corner of the contact surface between the chip and the solder layer has the largest stress at the end of the cycle, measuring 19.377 MPa. (3) The Engelmaier model predicts that the gadget will have a thermal fatigue life of 1928.67 h. (4) Expanding the layered solder area caused by any solder overflow mode may shorten the device's thermal fatigue life. The thermal fatigue life of a completely spilled solder is higher than that of a partially spilled solder.

Simulation of Single-Event Transient Effect for GaN High-Electron-Mobility Transistor.

A GaN high-electron-mobility transistor (HEMT) was simulated using the semiconductor simulation software Silvaco TCAD in this paper. By constructing a two-dimensional structure of GaN HEMT, combined with key models such as carrier mobility, the effects of a different state, different incidence position, different drain voltage, different LET values, and a different incidence angle on the single-event transient effect of GaN HEMT are simulated. LET stands for the linear energy transfer capacity of a particle, which refers to the amount of energy transferred by the particle to the irradiated substance on the unit path. The simulation results show that for GaN HEMTs, the single-event transient effect is more obvious when the device is in off-state than in on-state. The most sensitive location of GaN HEMTs to the single-event effect is in the region near the drain. The peak transient current increases with the increase in the drain bias and incident ion LET values. The drain charge collection time increases with the angle of incidence of heavy ion.

Thermal Performance Optimization of Integrated Microchannel Cooling Plate for IGBT Power Module.

In high-integration electronic components, the insulated-gate bipolar transistor (IGBT) power module has a high working temperature, which requires reasonable thermal analysis and a cooling process to improve the reliability of the IGBT module. This paper presents an investigation into the heat dissipation of the integrated microchannel cooling plate in the silicon carbide IGBT power module and reports the impact of the BL series micropump on the efficiency of the cooling plate. The IGBT power module was first simplified as an equivalent-mass block with a mass of 62.64 g, a volume of 15.27 cm3, a density of 4.10 g/cm3, and a specific heat capacity of 512.53 J/(kg·K), through an equivalent method. Then, the thermal performance of the microchannel cooling plate with a main channel and a secondary channel was analyzed and the design of experiment (DOE) method was used to provide three factors and three levels of orthogonal simulation experiments. The three factors included microchannel width, number of secondary inlets, and inlet diameter. The results show that the microchannel cooling plate significantly reduces the temperature of IGBT chips and, as the microchannel width, number of secondary inlets, and inlet diameter increase, the junction temperature of chips gradually decreases. The optimal structure of the cooling plate is a microchannel width of 0.58 mm, 13 secondary inlets, and an inlet diameter of 3.8 mm, and the chip-junction temperature of this structure is decreased from 677 °C to 77.7 °C. In addition, the BL series micropump was connected to the inlet of the cooling plate and the thermal performance of the microchannel cooling plate with a micropump was analyzed. The micropump increases the frictional resistance of fluid flow, resulting in an increase in chip-junction temperature to 110 °C. This work demonstrates the impact of micropumps on the heat dissipation of cooling plates and provides a foundation for the design of cooling plates for IGBT power modules.

Research on Surface Morphology of Gold Micro Bumps Based on Monte Carlo Method.

In advanced packaging technology, the micro bump has become an important means of chip stacking and wafer interconnection. The reliability of micro bumps, which plays an important role in mechanical support, electrical connection, signal transmission and heat dissipation, determines the quality of chip packaging. Surface morphological defects are one of the main factors affecting the reliability of micro bumps, which are closely related to materials and bonding process parameters. In this paper, the electrodeposition process of preparing gold bumps is simulated at the atomic scale using the Kinetic Monte Carlo method. The differences in surface morphology and roughness of the plated layer are studied from a microscopic perspective under different deposition parameters. The results show that the gold micro bumps prepared by electrodeposition have better surface quality under conditions of lower deposition voltage, lower ion concentration and higher plating temperature, which can provide significant guidance for engineering applications.

Research of Vertical via Based on Silicon, Ceramic and Glass.

With the increasing demand for high-density integration, low power consumption and high bandwidth, creating more sophisticated interconnection technologies is becoming increasingly crucial. Three-dimensional (3D) integration technology is known as the fourth-generation packaging technology beyond Moore's Law because of its advantages of low energy consumption, lightweight and high performance. Through-silicon via (TSV) is considered to be at the core of 3D integration because of its excellent electrical performance, lower power consumption, wider bandwidth, higher density, smaller overall size and lighter weight. Therefore, the particular emphasis of this review is the process flow of TSV technology. Among them, the research status of TSV hole etching, deep hole electroplating filling and chemical mechanical planarization (CMP) in TSV preparation process are introduced in detail. There are a multitude of inevitable defects in the process of TSV processing; thus, the stress problems and electrical characteristics that affect the reliability of TSV are summarized in this review. In addition, the process flow and process optimization status of through ceramic via (TCV) and through glass via (TGV) are discussed.

Effect of P-Type GaN Buried Layer on the Temperature of AlGaN/GaN HEMTs.

In this paper, a P-type GaN buried layer is introduced into the buffer layer of AlGaN/GaN HEMTs, and the effect of the P-type GaN buried layer on the device's temperature characteristics is studied using Silvaco TCAD software. The results show that, compared to the conventional device structure, the introduction of a P-type GaN buried layer greatly weakens the peak of the channel electric field between the gate and drain of the device. This leads to a more uniform electric field distribution, a substantial reduction in the lattice temperature of the device, and a more uniform temperature distribution. Therefore, the phenomenon of negative resistance caused by self-heating effect is significantly mitigated, while the breakdown performance of the device is also notably enhanced.

Defect Dipole Behaviors on the Strain Performances of Bismuth Sodium Titanate-Based Lead-Free Piezoceramics.

Bismuth sodium titanate (BNT)-based, lead-free piezoelectric materials have been extensively studied due to their excellent strain characteristics and environmental friendliness. In BNTs, the large strain (S) usually requires a relatively large electric field (E) excitation, resulting in a low inverse piezoelectric coefficient d33* (S/E). Moreover, the hysteresis and fatigue of strain in these materials have also been bottlenecks impeding the applications. The current common regulation method is chemical modification, which mainly focuses on forming a solid solution near the morphotropic phase boundary (MPB) by adjusting the phase transition temperature of the materials, such as BNT-BaTiO3, BNT-Bi0.5K0.5TiO3, etc., to obtain a large strain. Additionally, the strain regulation based on the defects introduced by the acceptor, donor, or equivalent dopant or the nonstoichiometry has proven effective, but its underlying mechanism is still ambiguous. In this paper, we review the generation of strain and then discuss it from the domain, volume, and boundary effect perspectives to understand the defect dipole behavior. The asymmetric effect caused by the coupling between defect dipole polarization and ferroelectric spontaneous polarization is expounded. Moreover, the defect effect on the conductive and fatigue properties of BNT-based solid solutions is described, which will affect the strain characteristics. The optimization approach is appropriately evaluated while there are still challenges in the full understanding of the defect dipoles and their strain output, in which further efforts are needed to achieve new breakthroughs in atomic-level insight.

Three-Dimensional Integrated Fan-Out Wafer-Level Package Micro-Bump Electromigration Study.

To meet the demands for miniaturization and multi-functional and high-performance electronics applications, the semiconductor industry has shifted its packaging approach to multi-chip vertical stacking. Among the advanced packaging technologies for high-density interconnects, the most persistent factor affecting their reliability is the electromigration (EM) problem on the micro-bump. The operating temperature and the operating current density are the main factors affecting the EM phenomenon. Therefore, when a micro-bump structure is in the electrothermal environment, the EM failure mechanism of the high-density integrated packaging structure must be studied. To investigate the relationship between loading conditions and EM failure time in micro-bump structures, this study established an equivalent model of the vertical stacking structure of fan-out wafer-level packages. Then, the electrothermal interaction theory was used to carry out numerical simulations in an electrothermal environment. Finally, the MTTF equation was invoked, with Sn63Pb37 as the bump material, and the relationship between the operating environment and EM lifetime was investigated. The results showed that the current aggregation was the location where the bump structure was most susceptible to EM failure. The accelerating effect of the temperature on the EM failure time was more obvious at a current density of 3.5 A/cm2, which was 27.51% shorter than 4.5 A/cm2 at the same temperature difference. When the current density exceeded 4.5 A/cm2, the change in the failure time was not obvious, and the maximum critical value of the micro-bump failure was 4 A/cm2~4.5 A/cm2.

The Study of the Reliability of Complex Components during the Electromigration Process.

With the increasing number of inputs and outputs, and the decreasing interconnection spacing, electrical interconnection failures caused by electromigration (EM) have attracted more and more attention. The electromigration reliability and failure mechanism of complex components were studied in this paper. The failure mechanism and reliability of complex components during the electromigration process were studied through the simulation and the experiment, which can overcome the limitation of experimental measurement at a micro-scale. The simulation results indicated that the solder joint has obvious current crowding at the current inlet, which will significantly enhance the electromigration effect. Based on the atomic flux divergence method, the void formation of solder joints can be effectively predicted, and life prediction can be more accurate than Black's equation. Experimental results indicated that the resistance of the daisy chain could be significantly increased with the process of void formation in the solder and corrosion of the leads. Moreover, the growth of intermetallic compounds can be obviously promoted under current stress. The main composition of the intermetallic compounds changes from almost entirely Cu5Sn6 to Cu5Sn6 and Cu3Sn; the cracks can be detected at the Cu3Sn layer. Specifically, the mean time to failure is 1065 h under 1.4 A current and 125 °C based on IPC-9701A guidelines.

Combined Effect of TID Radiation and Electrical Stress on NMOSFETs.

The combined effect of total ionizing dose (TID) and electrical stress is investigated on NMOSFETs. For devices bearing both radiation and electrical stress, the threshold voltage shift is smaller than those only bearing electrical stress, indicating that the combined effect alleviates the degradation of the devices. The H bond is broken during the radiation process, which reduces the participation of H atoms in the later stage of electrical stress, thereby reducing the degradation caused by electrical stress. The positive charges of the oxide layer generated by radiation neutralize part of the tunneling electrons caused by electrical stress, and consume some of the electrons that react with the H bond, resulting in weaker degradation. In addition, the positive charges in shallow trench isolation (STI) generated by radiation create parasitic leakage paths at the interfaces of STI/Si, which increase the leakage current and reduce the positive shift of the threshold voltage. The parasitic effect generated by the positive charges of STI makes the threshold voltage of the narrow-channel device degrade more, and due to the gate edge effect, the threshold voltage of short-channel devices degrades more.

Using Chiplet Encapsulation Technology to Achieve Processing-in-Memory Functions.

With the rapid development of 5G, artificial intelligence (AI), and high-performance computing (HPC), there is a huge increase in the data exchanged between the processor and memory. However, the "storage wall" caused by the von Neumann architecture severely limits the computational performance of the system. To efficiently process such large amounts of data and break up the "storage wall", it is necessary to develop processing-in-memory (PIM) technology. Chiplet combines processor cores and memory chips with advanced packaging technologies, such as 2.5D, 3 dimensions (3D), and fan-out packaging. This improves the quality and bandwidth of signal transmission and alleviates the "storage wall" problem. This paper reviews the Chiplet packaging technology that has achieved the function of PIM in recent years and analyzes some of its application results. First, the research status and development direction of PIM are presented and summarized. Second, the Chiplet packaging technologies that can realize the function of PIM are introduced, which are divided into 2.5D, 3D packaging, and fan-out packaging according to their physical form. Further, the form and characteristics of their implementation of PIM are summarized. Finally, this paper is concluded, and the future development of Chiplet in the field of PIM is discussed.

Height Uniformity Simulation and Experimental Study of Electroplating Gold Bump for 2.5D/3D Integrated Packaging.

With the rapid development of nano/micro technology for commercial electronics, the typical interconnection method could not satisfy the high power-density packaging requirement. The 2.5D/3D integrated packaging was seen as a promising technology for nano/micro systems. The gold (Au) bump was the frequently used bonding method for these systems because of its excellent thermal, electric, and mechanical performance. However, relatively little work has been performed to analyze its height uniformity. In this study, the simulation and experimental methods were used to analyze the Au bump height uniformity. Firstly, the electroplating process of Au bump under different flow field parameters was simulated by COMSOL software. The simulated results indicated that the Au+ concentration polarization was the significant reason that caused the non-uniform distribution of Au bump along the wafer radius. Meanwhile, the flow field parameters, such as inlet diameter, inlet flow, titanium (Ti), wire mesh height, and Ti wire mesh density, were optimized, and their values were 20 mm, 20 L/min, 12 mm, and 50%, respectively. Subsequently, the Au bump height uniformity under different current densities was analyzed through an experimental method based on these flow field parameters. The experimental results showed that the increases of current density would decrease the Au bump height uniformity. When the current density was 0.2 A/dm2, the average height, range, and deviance values of Au bump were 9.04 µm, 1.33 µm, and 0.43 µm, respectively, which could reach the requirement of high density and precision for 2.5D/3D integrated packaging.

Visualization and Heat Transfer Performance of Mini-Grooved Flat Heat Pipe Filled with Different Working Fluids.

Mini-grooved flat heat pipe (MGFHP) possesses the advantages of high compactness, no mechanical component, super thermal conductivity, and excellent temperature uniformity, which can meet the demand for electronic devices efficiently cooling. In this research, visual and heat transfer experiments were performed to investigate the flow and thermal characteristics inside the MGFHP. Fluid flow and distribution are observed to be quite different in the MGFHP containing different working fluids, which is affected by the physical properties of working fluid, the surface state of the grooved wick, and limited working space. Additionally, the input heat, working fluid type, filling ratio, and wettability obviously affect the thermal conductivity and temperature uniformity of the MGFHP. The deionized water-filled MGFHP possesses lower thermal resistance and higher heat transfer capacity than anhydrous ethanol or hexane filled MGFHP, especially for the copper oxide MGFHP filled with deionized water with a filling ratio of 1.0. Thermal resistance, maximum temperature, and temperature nonuniformity at the condensation section of deionized water-filled copper oxide MGFHP are lower than those of the original copper MGFHP by 31.1%, 3.7 °C, and 0.11 °C for the anhydrous ethanol filled MGFHP and 34.4%, 3.1 °C, and 0.13 °C for the hexane filled MGFHP, respectively.

A Method for Broadband Polyimide Permittivity Measurement of Silicon Interposer Applied for High Speed Digital Microsystem.

High-speed digital microsystems has emerged as one of the most important solutions for improving system performance, bandwidth, and power consumption. Based on mature micro-system processing technology, a material extraction approach for silicon interposer applied for high-speed digital microsystems was presented in order to obtain frequency-dependent precise material parameters. By combining microwave theory and mathematical model of iterative algorithm, the dielectric constant (Dk) and the dissipation factor (Df) of polyimide dielectric layer is acquired, which minimizes testing costs and streamlines testing process. The method is based on two-port transmission/reflection measurements. Vector Network Analyzer (VNA) is used to extract the scattering parameters with an extraction range of 1 MHz to 10 GHz. The algorithm is programmed using MATLAB. The observed Dk values at 2 GHz, 6 GHz, 8 GHz, and 10 GHz are, respectively, 3.22, 3.04, 2.96, 3.03, and 2.91, while the corresponding Df values are 0.021, 0.025, 0.026, 0.026, and 0.024. Finally, the complex permittivity derived is simulated and analyzed using Ansys HFSS. The results verify the validity of the theoretical method and proves that the values of the complex permittivity obtained by the method in this paper are reliable.

Molecular Dynamics Analysis of Graphene Nanoelectromechanical Resonators Based on Vacancy Defects.

Due to the limitation of graphene processing technology, the prepared graphene inevitably contains various defects. The defects will have a particular influence on the macroscopic characteristics of the graphene. In this paper, the defect-based graphene nanoresonators are studied. In this study, the resonant properties of graphene were investigated via molecular dynamic simulations. The effect of vacancy defects and hole defects at different positions, numbers, and concentrations on the resonance frequency of graphene nanoribbons was studied. The results indicated that single monatomic vacancy has no effect on graphene resonant frequency, and the concentration of the resonant frequency of graphene decreases almost linearly with the increase of single-atom vacancy concentration. When the vacancy concentration is 5%, the resonance frequency is reduced by 12.77% compared to the perfect graphene. Holes on the graphene cause the resonance frequency to decrease. As the circular hole defect is closer to the center of the graphene nanoribbon, not only does its resonant frequency increase, but the tuning range is also expanded accordingly. Under the external force of 10.715 nN, the resonant frequency of graphene reaches 429.57 GHz when the circular hole is located at the center of the graphene nanoribbon, which is 40 GHz lower than that of single vacancy defect graphene. When the circular hole is close to the fixed end of graphene, the resonant frequency is 379.62 GHz, which is 90 GHz lower than that of single vacancy graphene. When the hole defect is at the center of nanoribbon, the frequency tunable range of graphene reaches 120 GHz. The tunable frequency range of graphene is 100.12 GHz when the hole defect is near the fixed ends of the graphene nanoribbon. This work is of great significance for design and performance optimization of graphene-based nanoelectro-mechanical system (NEMS) resonators.

Hydrogen Storage Performance of γ-Graphdiyne Doped Li Based on First Principles for Micro/Nano.

The rapid development of micro/nano systems promotes the progress of micro energy storage devices. As one of the most significant representatives of micro energy storage devices, micro hydrogen fuel cells were initially studied by many laboratories and companies. However, hydrogen storage problems have restricted its further commercialization. The γ-graphdiyne (γ-GDY) has broad application prospects in the fields of energy storage and gas adsorption due to its unique structure with rigid nano-network and numerous uniform pores. However, the existence of various defects in γ-GDY caused varying degrees of influence on gas adsorption performance. In this study, Lithium (Li) was added into the intrinsic γ-GDY and vacancy defect γ-GDY (γ-VGDY) to obtain the Li-GDY and Li-VGDY, respectively. The first-principles calculation method was applied and the hydrogen storage performances of them were analysed. The results indicated that the best adsorption point of intrinsic γ-GDY is H2 point, which located at the centre of a large triangular hole of an acetylene chain. With large capacity hydrogen storage, doping Li atom could improve the hydrogen adsorption property of intrinsic γ-GDY; meanwhile, vacancy defect inspires the hydrogen storage performance further of Li-VGDY. The mass hydrogen storage density for Li2H56-GDY and Li2H56-VGDY model were 13.02% and 14.66%, respectively. Moreover, the Li2H56-GDY and Li2H56-VGDY model had same volumetric storage density, with values that could achieve 5.22 × 104 kg/m3.

Effect of Acceptor Traps in GaN Buffer Layer on Breakdown Performance of AlGaN/GaN HEMTs.

In this paper, Silvaco TCAD software is used to simulate the buffer traps in AlGaN/GaN high electron mobility transistors (HEMTs), and its effects on the breakdown performance and key parameters of the devices are investigated by changing the position and concentration of the acceptor traps in the buffer layer. The results show that with the increase of trap concentration, the traps capture electrons and reduce the off-state leakage current, which can improve breakdown voltage of the devices. At the same time, as the trap concentration increases, the ionized traps make a high additional electric field near the drain edge, leading to the decrease of breakdown voltage. With the combined two effects above, the breakdown voltage almost ultimately saturates. When the source-to-gate (Access-S) region in the GaN buffer layer is doped alone, the minimum and most linear leakage current for the same trap concentrations are obtained, and the additional electric field has a relatively small effect on the electric field peak near the drain as the ionized traps are furthest from drain. All these factors make the breakdown voltage increase more controllably with the Access-S region doping, and it is a more potential way to improve the breakdown performance.