RESUMEN
The decreasing-width, increasing-aspect-ratio RDL presents significant challenges to the design for reliability (DFR) of an advanced package. Therefore, this paper proposes an ML-based RDL modeling and simulation method. In the method, RDL was divided into blocks and subdivided into pixels of metal percentage, and the RDL was digitalized as tensors. Then, an ANN-based surrogate model was built and trained using a subset of tensors to predict the equivalent material properties of each block. Lastly, all blocks were transformed into elements for simulations. For validation, line bending simulations were conducted on an RDL, with the reaction force as an accuracy indicator. The results show that neglecting layout impact caused critical errors as the substrate thinned. According to the method, the reaction force error was 2.81% and the layout impact could be accurately considered with 200 × 200 elements. For application, the TCT maximum temperature state simulation was conducted on a CPU chip. The simulation indicated that for an advanced package, the maximum stress was more likely to occur in RDL rather than in bumps; both RDL and bumps were critically impacted by layouts, and RDL stress was also impacted by vias/bumps. The proposed method precisely concerned layout impacts with few resources, presenting an opportunity for efficient improvement.
RESUMEN
High-speed digital microsystems has emerged as one of the most important solutions for improving system performance, bandwidth, and power consumption. Based on mature micro-system processing technology, a material extraction approach for silicon interposer applied for high-speed digital microsystems was presented in order to obtain frequency-dependent precise material parameters. By combining microwave theory and mathematical model of iterative algorithm, the dielectric constant (Dk) and the dissipation factor (Df) of polyimide dielectric layer is acquired, which minimizes testing costs and streamlines testing process. The method is based on two-port transmission/reflection measurements. Vector Network Analyzer (VNA) is used to extract the scattering parameters with an extraction range of 1 MHz to 10 GHz. The algorithm is programmed using MATLAB. The observed Dk values at 2 GHz, 6 GHz, 8 GHz, and 10 GHz are, respectively, 3.22, 3.04, 2.96, 3.03, and 2.91, while the corresponding Df values are 0.021, 0.025, 0.026, 0.026, and 0.024. Finally, the complex permittivity derived is simulated and analyzed using Ansys HFSS. The results verify the validity of the theoretical method and proves that the values of the complex permittivity obtained by the method in this paper are reliable.
RESUMEN
In 3D-system packaging technologies, eutectic bonding is the key technology of multilayer chip stacking and vertical interconnection. Optimized from the aspects of the thickness of the electroplated metal layer, the pretreatment of the wafer surface removes the oxide layer, the mutual alignment between the wafers, the temperature of the wafer bonding, the uniformity of pressure and the deviation of the bonding process. Under the pretreatment conditions of plasma treatment and citric acid cleaning, no oxide layer was obtained on the metal surface. Cu/Sn bumps bonded under the condition of 0.135 Mpa, temperature of 280 °C, Sn thickness of 3-4 µm and a Cu-thickness of five micrometers. Bonded push crystal strength ≥18 kg/cm2, the average contact resistance of the bonding interface is about 3.35 mΩ, and the bonding yield is 100%. All performance indicators meet and exceed the industry standards.