Malakoplakia of urinary bladde: 3 cases reports and review.

OBJECTIVE: This study aims to explore the clinical diagnosis and treatment methods of bladder malakoplakia (MUB) to enhance the understanding of the disease. METHODS: A retrospective analysis of the diagnosis and treatment processes of three cases of MUB treated in our department was conducted. Relevant literature from both domestic and international sources was reviewed to provide a comprehensive analysis. RESULTS: All three patients underwent transurethral resection of bladder lesions combined with antibiotic therapy, and two of them received transurethral instillation of gemcitabine. There were two cases with two recurrences each, and one case with four recurrences, with the latter also concurrently presenting with unilateral ureteral malakoplakia. Postoperative pathology confirmed MUB in all three cases. Close follow-up revealed no significant recurrence in the patients. CONCLUSION: The effective diagnosis rate is increased by conducting multiple deep, repetitive, and randomly selected live tissue examinations. The definitive diagnosis of MUB relies on pathological histological examination. Treatment involving a combination of antibiotics and transurethral resection of bladder lesions proves to be effective. Exploring the use of bladder instillation of gemcitabine widens the spectrum of MUB treatment methods.

Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash.

The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash. The relationship between the drain-to-body potential (Vdb) of GIDL transistors and the increasing number of layers was studied to explain the reason for the self-adaption of the GIDL erase. The dynamics controlled by the drain-to-body and drain-to-gate potential contribute to the self-adaption of the GIDL erase. Increasing the number of layers leads to a longer duration of the maximum value of Vdb (Vdb_max), combined with the increased drain-to-gate potential, which enhances the GIDL current and further boosts channel potential to reach the same value at different positions of the NAND string. We proposed a method based on the correlation between the duration of Vdb_max and the number of layers to obtain the limited layers of the GIDL erase. The limited layers allowed are more than four times the number of layers used in the current simulation. Combining the novel method of dividing the channel into multi-regions with the asynchronous GIDL erase method will be useful for further stacking more layers in 3D NAND Flash.

Activation Enhancement and Grain Size Improvement for Poly-Si Channel Vertical Transistor by Laser Thermal Annealing in 3D NAND Flash.

The bit density is generally increased by stacking more layers in 3D NAND Flash. Lowering dopant activation of select transistors results from complex integrated processes. To improve channel dopant activation, the test structure of vertical channel transistors was used to investigate the influence of laser thermal annealing on dopant activation. The activation of channel doping by different thermal annealing methods was compared. The laser thermal annealing enhanced the channel activation rate by at least 23% more than limited temperature rapid thermal annealing. We then comprehensively explore the laser thermal annealing energy density on the influence of Poly-Si grain size and device performance. A clear correlation between grain size mean and grain size sigma, large grain size mean and sigma with large laser thermal annealing energy density. Large laser thermal annealing energy density leads to tightening threshold voltage and subthreshold swing distribution since Poly-Si grain size regrows for better grain size distribution with local grains optimization. As an enabler for next-generation technologies, laser thermal annealing will be highly applied in 3D NAND Flash for better device performance with stacking more layers, and opening new opportunities of novel 3D architectures in the semiconductor industry.

A Novel Capacitorless 1T DRAM with Embedded Oxide Layer.

A novel vertical dual surrounding gate transistor with embedded oxide layer is proposed for capacitorless single transistor DRAM (1T DRAM). The embedded oxide layer is innovatively used to improve the retention time by reducing the recombination rate of stored holes and sensing electrons. Based on TCAD simulations, the new structure is predicted to not only have the characteristics of fast access, random read and integration of 4F2 cell, but also to realize good retention and deep scaling. At the same time, the new structure has the potential of scaling compared with the conventional capacitorless 1T DRAM.

Application of a Hybrid Model of Big Data and BP Network on Fault Diagnosis Strategy for Microgrid.

Aiming at the characteristics of timely transmission, rapid update, and large magnitude of microgrid data, based on the large data samples generated by microgrid operation, a fault diagnosis and analysis method of microgrid systems supported by big data is proposed in this paper. The multisource joint feature vectors of microgrid are extracted using Wavelet transform, Rayleigh entropy, and big data technology, which combine short-circuit current and voltage. The extracted feature dataset is clustered and segmented to realize deep data mining. Combining BP neural network and big data, the fault diagnosis of microgrid is realized. The simulation results show that the BP neural network algorithm based on big data support can accurately identify the type and phase of internal faults in microgrid, which is more suitable for extracting the temporal characteristics of information and spatiotemporal correlation of data to realize the prediction of big data and solve the core problems in the analysis of big data of microgrid faults, and the accuracy is as high as 96.8%.

The Optimization of Gate All Around-L-Shaped Bottom Select Transistor in 3D NAND Flash Memory.

In this work, the GAA (Gate All Around) L-Shaped bottom select transistor (BSG) in 3D NAND Flash Memory has been investigated. Different methods are proposed to optimize its performance from viewpoints of process and structure. BSG in 3D NAND is a novel device structure with two connected transistors: one is horizontal MOSFET (regarded as convention MOSFET) and one is vertical MOSFET (regarded as GAA transistor). With implant dose increasing in vertical channel, BSG Vth has much more tighter Vt distribution, which is beneficial for boosting potential improvement and program disturbance suppression. Meanwhile, BSG corner rounding is proposed to improve the characteristic of BSG. Experiment and TCAD simulation data are matches quite well, giving a way to improve cell characteristics distribution and self-boosting potential control in high density 3D NAND array.