Robust control of a wind energy conversion system: FPGA real-time implementation.

This study employs an FPGA board to implement a robust control technique for wind energy conversion systems (WECS). This approach facilitates extensive testing and validation of the control system across diverse wind conditions, utilizing the FPGA's parallel processing capabilities and advanced control algorithms. This method ensures robustness against nonlinearities and system uncertainties. FPGA-in-the-loop (FIL) testing provides precise and effective simulation results, enabling rapid prototyping and iterative modifications of control algorithms. The effectiveness of the robust control strategy is confirmed by FIL findings, demonstrating significant improvements in WECS stability and efficiency. Furthermore, the study highlights the strategy's potential to enhance WECS reliability and efficiency in real-world applications.

A Device-on-Chip Solution for Real-Time Diffuse Correlation Spectroscopy Using FPGA.

Diffuse correlation spectroscopy (DCS) is a non-invasive technology for the evaluation of blood perfusion in deep tissue. However, it requires high computational resources for data analysis, which poses challenges in its implementation for real-time applications. To address the unmet need, we developed a novel device-on-chip solution that fully integrates all the necessary computational components needed for DCS. It takes the output of a photon detector and determines the blood flow index (BFI). It is implemented on a field-programmable gate array (FPGA) chip including a multi-tau correlator for the calculation of the temporal light intensity autocorrelation function and a DCS analyzer to perform the curve fitting operation that derives the BFI at a rate of 6000 BFIs/s. The FPGA DCS system was evaluated against a lab-standard DCS system for both phantom and cuff ischemia studies. The results indicate that the autocorrelation of the light correlation and BFI from both the FPGA DCS and the reference DCS matched well. Furthermore, the FPGA DCS system was able to achieve a measurement rate of 50 Hz and resolve pulsatile blood flow. This can significantly lower the cost and footprint of the computational components of DCS and pave the way for portable, real-time DCS systems.

Optimization of UWB indoor positioning based on hardware accelerated Fuzzy ISODATA.

With the development of wireless communication technology, Ultra-Wideband (UWB) has become an important solution for indoor positioning. In complex indoor environments, the influence of non-line-of-sight (NLOS) factors leads to increased positioning errors. To improve the positioning accuracy, fuzzy iterative self-organizing data analysis clustering algorithm (ISODATA) is introduced to process a large amount of UWB data to reduce the influence of NLOS factors, and to stabilize positioning error within 2 cm, enhances the accuracy of the positioning system. To further improve the running efficiency of the algorithm, FPGA is used to accelerate the key computational part of the algorithm, compared with running on the MATLAB platform, which improves the speed about 100 times, enhances the algorithm's computational speed dramatically.

Design and implementation of single DC-link based three-phase multilevel inverter with CB-PWM techniques.

Simulation and implementation of a single DC-link-based three-phase inverter are investigated in this article. The primary focus is on designing a single DC-link three-phase inverter for high power applications. Unlike conventional inverters that require 600 V to generate 400 V (RMS) at the output, the proposed system achieves this with only 330 V, facilitated by a 12-terminal 1:1 transformer. The system employs Proportional Integral (PI) and Neural Network (NN) controllers to optimize performance. Various Carrier-Based Pulse Width Modulation (CB-PWM) techniques, including Phase Disposition (PD), Phase Opposition Disposition (POD), and Alternative Phase Opposition Disposition (APOD), are implemented and evaluated based on Total Harmonics Distortion (THD) concerning the Modulation Index (MI) of the inverter. The proposed inverter achieves a THD reduction to 4.8%, demonstrating superior performance compared to recent studies. The system's performance is validated through extensive MATLAB/Simulink simulations and practical implementation using XILINX FPGA software, confirming the efficacy of the proposed design.

A novel fractional-order memristive Hopfield neural network for traveling salesman problem and its FPGA implementation.

This paper proposes a novel fractional-order memristive Hopfield neural network (HNN) to address traveling salesman problem (TSP). Fractional-order memristive HNN can efficiently converge to a globally optimal solution, while conventional HNN tends to become stuck at a local minimum in solving TSP. Incorporating fractional-order calculus and memristors gives the system long-term memory properties and complex chaotic characteristics, resulting in faster convergence speeds and shorter average distances in solving TSP. Moreover, a novel chaotic optimization algorithm based on fractional-order memristive HNN is designed for the calculation process to deal with mutual constraint between convergence accuracy and convergence speed, which circumvents random search and diminishes the rate of invalid solutions. Numerical simulations demonstrate the effectiveness and merits of the proposed algorithm. Furthermore, Field Programmable Gate Array (FPGA) technology is utilized to implement the proposed neural network.

Real-time execution of SNN models with synaptic plasticity for handwritten digit recognition on SIMD hardware.

Recent advancements in neuromorphic computing have led to the development of hardware architectures inspired by Spiking Neural Networks (SNNs) to emulate the efficiency and parallel processing capabilities of the human brain. This work focuses on testing the HEENS architecture, specifically designed for high parallel processing and biological realism in SNN emulation, implemented on a ZYNQ family FPGA. The study applies this architecture to the classification of digits using the well-known MNIST database. The image resolutions were adjusted to match HEENS' processing capacity. Results were compared with existing work, demonstrating HEENS' performance comparable to other solutions. This study highlights the importance of balancing accuracy and efficiency in the execution of applications. HEENS offers a flexible solution for SNN emulation, allowing for the implementation of programmable neural and synaptic models. It encourages the exploration of novel algorithms and network architectures, providing an alternative for real-time processing with efficient energy consumption.

A Human-Computer Interaction Strategy for An FPGA Platform Boosted Integrated "Perception-Memory" System Based on Electronic Tattoos and Memristors.

The integrated "perception-memory" system is receiving increasing attention due to its crucial applications in humanoid robots, as well as in the simulation of the human retina and brain. Here, a Field Programmable Gate Array (FPGA) platform-boosted system that enables the sensing, recognition, and memory for human-computer interaction is reported by the combination of ultra-thin Ag/Al/Paster-based electronic tattoos (AAP) and Tantalum Oxide/Indium Gallium Zinc Oxide (Ta2O5/IGZO)-based memristors. Notably, the AAP demonstrates exceptional capabilities in accommodating the strain caused by skin deformation, thanks to its unique structural design, which ensures a secure fit to the skin and enables the prolonged monitoring of physiological signals. By utilizing Ta2O5/IGZO as the functional layer, a high switching ratio is conferred to the memristor, and an integrated system for sensing, distinguishing, storing, and controlling the machine hand of multiple human physiological signals is constructed together with the AAP. Further, the proposed system implements emergency calls and smart homes using facial electromyogram signals and utilizing logical entailment to realize the control of the music interface. This innovative "perception-memory" integrated system not only serves the disabled, enhancing human-computer interaction but also provides an alternative avenue to enhance the quality of life and autonomy of individuals with disabilities.

An FPGA-based hardware accelerator supporting sensitive sequence homology filtering with profile hidden Markov models.

BACKGROUND: Sequence alignment lies at the heart of genome sequence annotation. While the BLAST suite of alignment tools has long held an important role in alignment-based sequence database search, greater sensitivity is achieved through the use of profile hidden Markov models (pHMMs). Here, we describe an FPGA hardware accelerator, called HAVAC, that targets a key bottleneck step (SSV) in the analysis pipeline of the popular pHMM alignment tool, HMMER. RESULTS: The HAVAC kernel calculates the SSV matrix at 1739 GCUPS on a ∼  $3000 Xilinx Alveo U50 FPGA accelerator card, ∼  227× faster than the optimized SSV implementation in nhmmer. Accounting for PCI-e data transfer data processing, HAVAC is 65× faster than nhmmer's SSV with one thread and 35× faster than nhmmer with four threads, and uses ∼  31% the energy of a traditional high end Intel CPU. CONCLUSIONS: HAVAC demonstrates the potential offered by FPGA hardware accelerators to produce dramatic speed gains in sequence annotation and related bioinformatics applications. Because these computations are performed on a co-processor, the host CPU remains free to simultaneously compute other aspects of the analysis pipeline.

Development of a Dynamically Re-Configurable Radio-Frequency Interference Detection System for L-Band Microwave Radiometers.

Real-Time RFI Detection and Flagging (RT-RDF) for microwave radiometers is a versatile new FPGA algorithm designed to detect and flag Radio-Frequency Interference (RFI) in microwave radiometers. This block utilizes computationally-efficient techniques to identify and analyze RF signals, allowing the system to take appropriate measures to mitigate interference and maintain reliable performance. With L-Band microwave radiometry as the main application, this RFI detection algorithm focuses on the Kurtogram and Spectrogram to detect non-Gaussian behavior. To gain further modularity, an FFT-based filter bank is used to divide the receiver's bandwidth into several sub-bands within the band of interest of the instrument, depending on the application. Multiple blanking strategies can then be applied in each band using the provided detection flags. The algorithm can be re-configured in the field, for example with dynamic integration times to support operation in different environments, or configurable thresholds to account for variable RFI environments. A validation and testing campaign has been performed on multiple scenarios with the ARIEL commercial microwave radiometer, and the results confirm the excellent performance of the system.

LMI-Based MPC Design Applied to the Single-Phase PWM Inverter with LC Filter under Uncertain Parameters.

This work proposes a design methodology for predictive control applied to the single-phase PWM inverter with an LC filter. In the design, we considered that the PWM inverter has parametric uncertainties in the filter inductance and output load resistance. The control system purpose is to track a sinusoidal signal at the inverter output. The designed control system with an embedded integrator uses the principle of receding horizon control, which underpinned predictive control. The methodology was described by linear matrix inequalities, which can be solved efficiently using convex programming techniques, and the optimal solution is obtained. MATLAB-Simulink and real-time FPGA-in-the-loop simulations illustrate the viability of the proposed control system. The LMI-based MPC reveals an effective performance for tracking of a sinusoidal reference signal and disturbance rejection of input voltage and load perturbations for the inverter subject to uncertainties.

SHA-256 Hardware Proposal for IoT Devices in the Blockchain Context.

This work proposes an implementation of the SHA-256, the most common blockchain hash algorithm, on a field-programmable gate array (FPGA) to improve processing capacity and power saving in Internet of Things (IoT) devices to solve security and privacy issues. This implementation presents a different approach than other papers in the literature, using clustered cores executing the SHA-256 algorithm in parallel. Details about the proposed architecture and an analysis of the resources used by the FPGA are presented. The implementation achieved a throughput of approximately 1.4 Gbps for 16 cores on a single FPGA. Furthermore, it saved dynamic power, using almost 1000 times less compared to previous works in the literature, making this proposal suitable for practical problems for IoT devices in blockchain environments. The target FPGA used was the Xilinx Virtex 6 xc6vlx240t-1ff1156.

Hybrid Filtering Compensation Algorithm for Suppressing Random Errors in MEMS Arrays.

To solve the high error phenomenon of microelectromechanical systems (MEMS) due to their poor signal-to-noise ratio, this paper proposes an online compensation algorithm wavelet threshold back-propagation neural network (WT-BPNN), based on a neural network and designed to effectively suppress the random error of MEMS arrays. The algorithm denoises MEMS and compensates for the error using a back propagation neural network (BPNN). To verify the feasibility of the proposed algorithm, we deployed it in a ZYNQ-based MEMS array hardware. The experimental results showed that the zero-bias instability, angular random wander, and angular velocity random wander of the gyroscope were improved by about 12 dB, 10 dB, and 7 dB, respectively, compared with the original device in static scenarios, and the dispersion of the output data was reduced by about 8 dB in various dynamic environments, which effectively verified the robustness and feasibility of the algorithm.

An Ultralow-Power Real-Time Machine Learning Based fNIRS Motion Artifacts Detection.

Due to iterative matrix multiplications or gradient computations, machine learning modules often require a large amount of processing power and memory. As a result, they are often not feasible for use in wearable devices, which have limited processing power and memory. In this study, we propose an ultralow-power and real-time machine learning-based motion artifact detection module for functional near-infrared spectroscopy (fNIRS) systems. We achieved a high classification accuracy of 97.42%, low field-programmable gate array (FPGA) resource utilization of 38354 lookup tables and 6024 flip-flops, as well as low power consumption of 0.021 W in dynamic power. These results outperform conventional CPU support vector machine (SVM) methods and other state-of-the-art SVM implementations. This study has demonstrated that an FPGA-based fNIRS motion artifact classifier can be exploited while meeting low power and resource constraints, which are crucial in embedded hardware systems while keeping high classification accuracy.

An Edge Computing System with AMD Xilinx FPGA AI Customer Platform for Advanced Driver Assistance System.

The convergence of edge computing systems with Field-Programmable Gate Array (FPGA) technology has shown considerable promise in enhancing real-time applications across various domains. This paper presents an innovative edge computing system design specifically tailored for pavement defect detection within the Advanced Driver-Assistance Systems (ADASs) domain. The system seamlessly integrates the AMD Xilinx AI platform into a customized circuit configuration, capitalizing on its capabilities. Utilizing cameras as input sensors to capture road scenes, the system employs a Deep Learning Processing Unit (DPU) to execute the YOLOv3 model, enabling the identification of three distinct types of pavement defects with high accuracy and efficiency. Following defect detection, the system efficiently transmits detailed information about the type and location of detected defects via the Controller Area Network (CAN) interface. This integration of FPGA-based edge computing not only enhances the speed and accuracy of defect detection, but also facilitates real-time communication between the vehicle's onboard controller and external systems. Moreover, the successful integration of the proposed system transforms ADAS into a sophisticated edge computing device, empowering the vehicle's onboard controller to make informed decisions in real time. These decisions are aimed at enhancing the overall driving experience by improving safety and performance metrics. The synergy between edge computing and FPGA technology not only advances ADAS capabilities, but also paves the way for future innovations in automotive safety and assistance systems.

Artificial cerebellum on FPGA: realistic real-time cerebellar spiking neural network model capable of real-world adaptive motor control.

The cerebellum plays a central role in motor control and learning. Its neuronal network architecture, firing characteristics of component neurons, and learning rules at their synapses have been well understood in terms of anatomy and physiology. A realistic artificial cerebellum with mimetic network architecture and synaptic plasticity mechanisms may allow us to analyze cerebellar information processing in the real world by applying it to adaptive control of actual machines. Several artificial cerebellums have previously been constructed, but they require high-performance hardware to run in real-time for real-world machine control. Presently, we implemented an artificial cerebellum with the size of 104 spiking neuron models on a field-programmable gate array (FPGA) which is compact, lightweight, portable, and low-power-consumption. In the implementation three novel techniques are employed: (1) 16-bit fixed-point operation and randomized rounding, (2) fully connected spike information transmission, and (3) alternative memory that uses pseudo-random number generators. We demonstrate that the FPGA artificial cerebellum runs in real-time, and its component neuron models behave as those in the corresponding artificial cerebellum configured on a personal computer in Python. We applied the FPGA artificial cerebellum to the adaptive control of a machine in the real world and demonstrated that the artificial cerebellum is capable of adaptively reducing control error after sudden load changes. This is the first implementation and demonstration of a spiking artificial cerebellum on an FPGA applicable to real-world adaptive control. The FPGA artificial cerebellum may provide neuroscientific insights into cerebellar information processing in adaptive motor control and may be applied to various neuro-devices to augment and extend human motor control capabilities.

Hardware Acceleration of Digital Pulse Shape Analysis Using FPGAs.

The BC501A sensor is a liquid scintillator frequently used in nuclear physics for detecting fast neutrons. This paper describes a hardware implementation of digital pulse shape analysis (DPSA) for real-time analysis. DPSA is an algorithm that extracts the physically relevant parameters from the detected BC501A signals. The hardware solution is implemented in a MicroTCA system that provides the physical, mechanical, electrical, and cooling support for an AMC board (NAMC-ZYNQ-FMC) with a Xilinx ZYNQ Ultrascale-MP SoC. The Xilinx FPGA programmable logic implements a JESD204B interface to high-speed ADCs. The physical and datalink JESD204B layers are implemented using hardware description language (HDL), while the Xilinx high-level synthesis language (HLS) is used for the transport and application layers. The DPSA algorithm is a JESD204B application layer that includes a FIR filter and a constant fraction discriminator (CFD) function, a baseline calculation function, a peak detection function, and an energy calculation function. This architecture achieves an analysis mean time of less than 100 µs per signal with an FPGA resource utilization of about 50% of its most used resources. This paper presents a high-performance DPSA embedded system that interfaces with a 1 GS/s ADC and performs accurate calculations with relatively low latency.

A Versatile Approach for Adaptive Grid Mapping and Grid Flex-Graph Exploration with a Field-Programmable Gate Array-Based Robot Using Hardware Schemes.

Robotic exploration in dynamic and complex environments requires advanced adaptive mapping strategies to ensure accurate representation of the environments. This paper introduces an innovative grid flex-graph exploration (GFGE) algorithm designed for single-robot mapping. This hardware-scheme-based algorithm leverages a combination of quad-grid and graph structures to enhance the efficiency of both local and global mapping implemented on a field-programmable gate array (FPGA). This novel research work involved using sensor fusion to analyze a robot's behavior and flexibility in the presence of static and dynamic objects. A behavior-based grid construction algorithm was proposed for the construction of a quad-grid that represents the occupancy of frontier cells. The selection of the next exploration target in a graph-like structure was proposed using partial reconfiguration-based frontier-graph exploration approaches. The complete exploration method handles the data when updating the local map to optimize the redundant exploration of previously explored nodes. Together, the exploration handles the quadtree-like structure efficiently under dynamic and uncertain conditions with a parallel processing architecture. Integrating several algorithms into indoor robotics was a complex process, and a Xilinx-based partial reconfiguration approach was used to prevent computing difficulties when running many algorithms simultaneously. These algorithms were developed, simulated, and synthesized using the Verilog hardware description language on Zynq SoC. Experiments were carried out utilizing a robot based on a field-programmable gate array (FPGA), and the resource utilization and power consumption of the device were analyzed.

Real-Time Direction Judgment System for Dual-Frequency Laser Interferometer.

Current real-time direction judgment systems are inaccurate and insensitive, as well as limited by the sampling rate of analog-to-digital converters. To address this problem, we propose a dynamic real-time direction judgment system based on an integral dual-frequency laser interferometer and field-programmable gate array technology. The optoelectronic signals resulting from the introduction of a phase subdivision method based on the amplitude resolution of the laser interferometer when measuring displacement are analyzed. The proposed system integrates the optoelectronic signals to increase the accuracy of its direction judgments and ensures these direction judgments are made in real time by dynamically controlling the integration time. Several experiments were conducted to verify the performance of the proposed system. The results show that, compared with current real-time direction judgment systems, the proposed system makes accurate judgements during low-speed motions and can update directions within 0.125 cycles of the phase difference change at different speeds. Moreover, a sweep frequency experiment confirmed the system's ability to effectively judge dynamic directions. The proposed system is capable of accurate and real-time directional judgment during low-speed movements of a table in motion.

FPGA-based fast bin-ratio spiking ensemble network for radioisotope identification.

In this work, we demonstrate the training, conversion, and implementation flow of an FPGA-based bin-ratio ensemble spiking neural network applied for radioisotope identification. The combination of techniques including learned step quantisation (LSQ) and pruning facilitated the implementation by compressing the network's parameters down to 30% yet retaining the accuracy of 97.04% with an accuracy loss of less than 1%. Meanwhile, the proposed ensemble network of 20 3-layer spiking neural networks (SNNs), which incorporates 1160 spiking neurons, only needs 334 µs for a single inference with the given clock frequency of 100 MHz. Under such optimisation, this FPGA implementation in an Artix-7 board consumes 157 µJ per inference by estimation.

Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation.

In signal processing applications, the multipliers are essential component of arithmetic functional units in many applications, like digital signal processors, image/video processing, Machine Learning, Cryptography and Arithmetic & Logical units (ALU). In recent years, Profuse multipliers are there. In that, Vedic multiplier is one of the high-performance multiplications and it is used to signal/image processing applications. In order to ameliorate the performance of this multiplier further, by proposed a novel multiplier using hybrid compressor. The proposed hybrid compressor-based multiplier is designed and implemented in Field programmable Gate Array (FPGA-spartan 6). The synthesis result shows that the speed of proposed hybrid compressor-based multiplier gets improved as compared to Array multiplier (35.83%), Wallace tree multiplier (34.58%), Vedic Multiplier based on Carry look ahead adder (CLA) (28.49%), Vedic Multiplier based on Ripple carry adder (RCA) (20.65%), Booth Multiplication (21.65%) and Vedic Multiplication based on Han-Carlson Adder (HCA) (20.10%) and Hybrid multiplier using Carry Select Adder (CSELA) (17.81%) and Hybrid Vedic Multiplier (7.15%).