A semiconducting supramolecular Co(II)-metallogel based resistive random access memory (RRAM) design with good endurance capabilities.

A highly efficient approach for synthesizing a supramolecular metallogel of Co(II) ions, denoted as CoA-TA, has been established under room temperature and atmospheric pressure conditions. This method employs the metal-coordinating organic ligand benzene-1,3,5-tricarboxylic acid as a low molecular weight gelator (LMWG) in DMF solvent. A comprehensive analysis of the mechanical properties of the resulting supramolecular Co(II)-metallogel was conducted through rheological investigation, considering angular frequency and thixotropic study. The hierarchical rocky network structure of the supramolecular Co(II)-metallogel was unveiled using field emission scanning electron microscopy (FESEM). Transmission electron microscopic (TEM) analysis showed rod-shaped structures via low-magnification high angle annular dark field (HAADF) bright field scanning transmission electron microscopic (STEM) imaging, while energy dispersive X-ray (EDX) elemental mapping confirmed its primary chemical constituents. The formation mechanism of the metallogel was examined via fourier transform infrared spectroscopy (FTIR) spectroscopy. The nature of the synthesized CoA-TA metallogel was affirmed through powder X-ray diffraction (PXRD) analysis. Furthermore, this study involved fabrication of Schottky diode structures in a metal-semiconductor-metal geometry based on cobalt(II) metallogel (CoA-TA), enabling observation of charge transport behavior. Remarkably, a resistive random access memory (RRAM) device utilizing cobalt(II) metallohydrogel (CoA-TA) demonstrated bipolar resistive switching at room temperature and under ambient conditions. The switching mechanism was investigated, revealing the formation and rupture of conductive filaments between metal electrodes that govern the resistive switching behavior. This RRAM device exhibited an impressive ON/OFF ratio (~ 414) and exceptional endurance over 5000 switching cycles. These structures offer great potential for diverse applications such as non-volatile memory design, neuromorphic computing, flexible electronics and optoelectronics. Their advantages lie in their fabrication process, reliable resistive switching behavior and overall performance stability.

LRMP: Layer Replication with Mixed Precision for spatial in-memory DNN accelerators.

In-memory computing (IMC) with non-volatile memories (NVMs) has emerged as a promising approach to address the rapidly growing computational demands of Deep Neural Networks (DNNs). Mapping DNN layers spatially onto NVM-based IMC accelerators achieves high degrees of parallelism. However, two challenges that arise in this approach are the highly non-uniform distribution of layer processing times and high area requirements. We propose LRMP, a method to jointly apply layer replication and mixed precision quantization to improve the performance of DNNs when mapped to area-constrained IMC accelerators. LRMP uses a combination of reinforcement learning and mixed integer linear programming to search the replication-quantization design space using a model that is closely informed by the target hardware architecture. Across five DNN benchmarks, LRMP achieves 2.6-9.3× latency and 8-18× throughput improvement at minimal (<1%) degradation in accuracy.

Reconfigurable Selector-Free All-Optical Controlled Neuromorphic Memristor for In-Memory Sensing and Reservoir Computing.

Recently, the rising demand for data-based applications has driven the convergence of image sensing, memory, and computing unit interfaces. While specialized electronic hardware has spurred advancements in the in-memory and in-sensor computing, integrating the entire signal-processing chain into a single device still faces significant challenges. Here, a reconfigurable all-optical controlled memristor with the selector-free feature is demonstrated. The conductance of the device can be controlled within the pure light domain, which enables it to integrate sensing, memory, and computing together. The integrate-and-fire behavior is also realized through electrical stimuli. Furthermore, the device exhibits an excellent rectifying ratio and nonlinearity to overcome the sneak current. Finally, an in-memory sensing and computing architecture is realized through reservoir computing based on neuron and synaptic functions mimicked by the proposed device. Such an all-in-one paradigm facilitates the computing architecture with low energy consumption, low latency, and reduced hardware complexity.

Ferroelectric materials for neuroinspired computing applications.

In recent years, the emergence of numerous applications of artificial intelligence (AI) has sparked a new technological revolution. These applications include facial recognition, autonomous driving, intelligent robotics, and image restoration. However, the data processing and storage procedures in the conventional von Neumann architecture are discrete, which leads to the "memory wall" problem. As a result, such architecture is incompatible with AI requirements for efficient and sustainable processing. Exploring new computing architectures and material bases is therefore imperative. Inspired by neurobiological systems, in-memory and in-sensor computing techniques provide a new means of overcoming the limitations inherent in the von Neumann architecture. The basis of neural morphological computation is a crossbar array of high-density, high-efficiency non-volatile memory devices. Among the numerous candidate memory devices, ferroelectric memory devices with non-volatile polarization states, low power consumption and strong endurance are expected to be ideal candidates for neuromorphic computing. Further research on the complementary metal-oxide-semiconductor (CMOS) compatibility for these devices is underway and has yielded favorable results. Herein, we first introduce the development of ferroelectric materials as well as their mechanisms of polarization reversal and detail the applications of ferroelectric synaptic devices in artificial neural networks. Subsequently, we introduce the latest developments in ferroelectrics-based in-memory and in-sensor computing. Finally, we review recent works on hafnium-based ferroelectric memory devices with CMOS process compatibility and give a perspective for future developments.

A linear compensation method for inference accuracy improvement of memristive in-memory computing.

Memristive computing system (MCS), with the feature of in-memory computing capability, for artificial neural networks (ANNs) deployment showing low power and massive parallelism, is a promising alternative for traditional Von-Neumann architecture computing system. However, because of the various non-idealities of both peripheral circuits and memristor array, the performance of the practical MCS tends to be significantly reduced. In this work, a linear compensation method (LCM) is proposed for the performance improvement of MCS under the effect of non-idealities. By considering the effects of various non-ideal states in the MCS as a whole, the output error of the MCS under different conditions is investigated. Then, a mathematic model for the output error is established based on the experimental data. Furthermore, the MCS is researched at the physical circuit level as well, in order to analyze the specific way in which the non-idealities affect the output current. Finally, based on the established mathematical model, the LCM output current is compensated in real time to improve the system performance. The effectiveness of LCM is verified and showing outstanding performance in the residual neural network-34 network architecture, which is easily affected by the non-idealities in hardware. The proposed LCM can be naturally integrated into the operation processes of MCS, paving the way for optimizing the deployment on generic ANN hardware based on the memristor.

Bi-Directional and Operand-Controllable In-Memory Computing for Boolean Logic and Search Operations with Row and Column Directional SRAM (RC-SRAM).

The von Neumann architecture is no longer sufficient for handling large-scale data. In-memory computing has emerged as the potent method for breaking through the memory bottleneck. A new 10T SRAM bitcell with row and column control lines called RC-SRAM is proposed in this article. The architecture based on RC-SRAM can achieve bi-directional and operand-controllable logic-in-memory and search operations through different signal configurations, which can comprehensively respond to various occasions and needs. Moreover, we propose threshold-controlled logic gates for sensing, which effectively reduces the circuit area and improves accuracy. We validate the RC-SRAM with a 28 nm CMOS technology, and the results show that the circuits are not only full featured and flexible for customization but also have a significant increase in the working frequency. At VDD = 0.9 V and T = 25 °C, the bi-directional search frequency is up to 775 MHz and 567 MHz, and the speeds for row and column Boolean logic reach 759 MHz and 683 MHz.

Ternary Content-Addressable Memory Based on a Single Two-Dimensional Transistor for Memory-Augmented Learning.

Ternary content-addressable memory (TCAM) is promising for data-intensive artificial intelligence applications due to its large-scale parallel in-memory computing capabilities. However, it is still challenging to build a reliable TCAM cell from a single circuit component. Here, we demonstrate a single transistor TCAM based on a floating-gate two-dimensional (2D) ambipolar MoTe2 field-effect transistor with graphene contacts. Our bottom graphene contacts scheme enables gate modulation of the contact Schottky barrier heights, facilitating carrier injection for both electrons and holes. The 2D nature of our channel and contact materials provides device scaling potentials beyond silicon. By integration with a floating-gate stack, a highly reliable nonvolatile memory is achieved. Our TCAM cell exhibits a resistance ratio larger than 1000 and symmetrical complementary states, allowing the implementation of large-scale TCAM arrays. Finally, we show through circuit simulations that in-memory Hamming distance computation is readily achievable based on our TCAM with array sizes up to 128 cells.

Ionic Photovoltaics-in-Memory in van der Waals Material.

The photovoltaic effect is gaining growing attention in the optoelectronics field due to its low power consumption, sustainable nature, and high efficiency. However, the photovoltaic effects hitherto reported are hindered by the stringent band-alignment requirement or inversion symmetry-breaking, and are challenging for achieving multifunctional photovoltaic properties (such as reconfiguration, nonvolatility, and so on). Here, a novel ionic photovoltaic effect in centrosymmetric CdSb2Se3Br2 that can overcome these limitations is demonstrated. The photovoltaic effect displays significant anisotropy, with the photocurrent being most apparent along the CdBr2 chains while absent perpendicular to them. Additionally, the device shows electrically-induced nonvolatile photocurrent switching characteristics. The photovoltaic effect is attributed to the modulation of the built-in electric field through the migration of Br ions. Using these unique photovoltaic properties, a highly secure circuit with electrical and optical keys is successfully implemented. The findings not only broaden the understanding of the photovoltaic mechanism, but also provide a new material platform for the development of in-memory sensing and computing devices.

Reservoir computing with a random memristor crossbar array.

Physical implementations of reservoir computing (RC) based on the emerging memristors have become promising candidates of unconventional computing paradigms. Traditionally, sequential approaches by time-multiplexing volatile memristors have been prevalent because of their low hardware overhead. However, they suffer from the problem of speed degradation and fall short of capturing the spatial relationship between the time-domain inputs. Here, we explore a new avenue for RC using memristor crossbar arrays with device-to-device variations, which serve as physical random weight matrices of the reservoir layers, enabling faster computation thanks to the parallelism of matrix-vector multiplication as an intensive operation in RC. To achieve this new RC architecture, ultralow-current, self-selective memristors are fabricated and integrated without the need of transistors, showing greater potential of high scalability and three-dimensional integrability compared to the previous realizations. The information processing ability of our RC system is demonstrated in asks of recognizing digit images and waveforms. This work indicates that the 'nonidealities' of the emerging memristor devices and circuits are a useful source of inspiration for new computing paradigms.

New-Generation Ferroelectric AlScN Materials.

Ferroelectrics have great potential in the field of nonvolatile memory due to programmable polarization states by external electric field in nonvolatile manner. However, complementary metal oxide semiconductor compatibility and uniformity of ferroelectric performance after size scaling have always been two thorny issues hindering practical application of ferroelectric memory devices. The emerging ferroelectricity of wurtzite structure nitride offers opportunities to circumvent the dilemma. This review covers the mechanism of ferroelectricity and domain dynamics in ferroelectric AlScN films. The performance optimization of AlScN films grown by different techniques is summarized and their applications for memories and emerging in-memory computing are illustrated. Finally, the challenges and perspectives regarding the commercial avenue of ferroelectric AlScN are discussed.

Nondefective Vacancy Enhanced Resistive Switching Reliability in Emergent van der Waals Metal Phosphorus Trisulfide-Based Memristive In-Memory Computing Hardware.

Two-dimensional-material-based memristors are emerging as promising enablers of new computing systems beyond von Neumann computers. However, the most studied anion-vacancy-enabled transition metal dichalcogenide memristors show many undesirable performances, e.g., high leakage currents, limited memory windows, high programming currents, and limited endurance. Here, we demonstrate that the emergent van der Waals metal phosphorus trisulfides with unconventional nondefective vacancy provide a promising paradigm for high-performance memristors. The different vacancy types (i.e., defective and nondefective vacancies) induced memristive discrepancies are uncovered. The nondefective vacancies can provide an ultralow diffusion barrier and good memristive structure stability giving rise to many desirable memristive performances, including high off-state resistance of 1012 Ω, pA-level programming currents, large memory window up to 109, more than 7-bit conductance states, and good endurance. Furthermore, a high-yield (94%) memristor crossbar array is fabricated and implements multiple image processing successfully, manifesting the potential for in-memory computing hardware.

DAM SRAM CORE: An Efficient High-Speed and Low-Power CIM SRAM CORE Design for Feature Extraction Convolutional Layers in Binary Neural Networks.

This article proposes a novel design for an in-memory computing SRAM, the DAM SRAM CORE, which integrates storage and computational functionality within a unified 11T SRAM cell and enables the performance of large-scale parallel Multiply-Accumulate (MAC) operations within the SRAM array. This design not only improves the area efficiency of the individual cells but also realizes a compact layout. A key highlight of this design is its employment of a dynamic aXNOR-based computation mode, which significantly reduces the consumption of both dynamic and static power during the computational process within the array. Additionally, the design innovatively incorporates a self-stabilizing voltage gradient quantization circuit, which enhances the computational accuracy of the overall system. The 64 × 64 bit DAM SRAM CORE in-memory computing core was fabricated using the 55 nm CMOS logic process and validated via simulations. The experimental results show that this core can deliver 5-bit output results with 1-bit input feature data and 1-bit weight data, while maintaining a static power consumption of 0.48 mW/mm2 and a computational power consumption of 11.367 mW/mm2. This showcases its excellent low-power characteristics. Furthermore, the core achieves a data throughput of 109.75 GOPS and exhibits an impressive energy efficiency of 21.95 TOPS/W, which robustly validate the effectiveness and advanced nature of the proposed in-memory computing core design.

Emerging 2D Ferroelectric Devices for In-Sensor and In-Memory Computing.

The quantity of sensor nodes within current computing systems is rapidly increasing in tandem with the sensing data. The presence of a bottleneck in data transmission between the sensors, computing, and memory units obstructs the system's efficiency and speed. To minimize the latency of data transmission between units, novel in-memory and in-sensor computing architectures are proposed as alternatives to the conventional von Neumann architecture, aiming for data-intensive sensing and computing applications. The integration of 2D materials and 2D ferroelectric materials has been expected to build these novel sensing and computing architectures due to the dangling-bond-free surface, ultra-fast polarization flipping, and ultra-low power consumption of the 2D ferroelectrics. Here, the recent progress of 2D ferroelectric devices for in-sensing and in-memory neuromorphic computing is reviewed. Experimental and theoretical progresses on 2D ferroelectric devices, including passive ferroelectrics-integrated 2D devices and active ferroelectrics-integrated 2D devices, are reviewed followed by the integration of perception, memory, and computing application. Notably, 2D ferroelectric devices have been used to simulate synaptic weights, neuronal model functions, and neural networks for image processing. As an emerging device configuration, 2D ferroelectric devices have the potential to expand into the sensor-memory and computing integration application field, leading to new possibilities for modern electronics.

A comprehensive review of advanced trends: from artificial synapses to neuromorphic systems with consideration of non-ideal effects.

A neuromorphic system is composed of hardware-based artificial neurons and synaptic devices, designed to improve the efficiency of neural computations inspired by energy-efficient and parallel operations of the biological nervous system. A synaptic device-based array can compute vector-matrix multiplication (VMM) with given input voltage signals, as a non-volatile memory device stores the weight information of the neural network in the form of conductance or capacitance. However, unlike software-based neural networks, the neuromorphic system unavoidably exhibits non-ideal characteristics that can have an adverse impact on overall system performance. In this study, the characteristics required for synaptic devices and their importance are discussed, depending on the targeted application. We categorize synaptic devices into two types: conductance-based and capacitance-based, and thoroughly explore the operations and characteristics of each device. The array structure according to the device structure and the VMM operation mechanism of each structure are analyzed, including recent advances in array-level implementation of synaptic devices. Furthermore, we reviewed studies to minimize the effect of hardware non-idealities, which degrades the performance of hardware neural networks. These studies introduce techniques in hardware and signal engineering, as well as software-hardware co-optimization, to address these non-idealities through compensation approaches.

Oscillatory Neural Network-Based Ising Machine Using 2D Memristors.

Neural networks are increasingly used to solve optimization problems in various fields, including operations research, design automation, and gene sequencing. However, these networks face challenges due to the nondeterministic polynomial time (NP)-hard issue, which results in exponentially increasing computational complexity as the problem size grows. Conventional digital hardware struggles with the von Neumann bottleneck, the slowdown of Moore's law, and the complexity arising from heterogeneous system design. Two-dimensional (2D) memristors offer a potential solution to these hardware challenges, with their in-memory computing, decent scalability, and rich dynamic behaviors. In this study, we explore the use of nonvolatile 2D memristors to emulate synapses in a discrete-time Hopfield neural network, enabling the network to solve continuous optimization problems, like finding the minimum value of a quadratic polynomial, and tackle combinatorial optimization problems like Max-Cut. Additionally, we coupled volatile memristor-based oscillators with nonvolatile memristor synapses to create an oscillatory neural network-based Ising machine, a continuous-time analog dynamic system capable of solving combinatorial optimization problems including Max-Cut and map coloring through phase synchronization. Our findings demonstrate that 2D memristors have the potential to significantly enhance the efficiency, compactness, and homogeneity of integrated Ising machines, which is useful for future advances in neural networks for optimization problems.

Synergistically Modulating Conductive Filaments in Ion-Based Memristors for Enhanced Analog In-Memory Computing.

Memristors offer a promising solution to address the performance and energy challenges faced by conventional von Neumann computer systems. Yet, stochastic ion migration in conductive filament often leads to an undesired performance tradeoff between memory window, retention, and endurance. Herein, a robust memristor based on oxygen-rich SnO2 nanoflowers switching medium, enabled by seed-mediated wet chemistry, to overcome the ion migration issue for enhanced analog in-memory computing is reported. Notably, the interplay between the oxygen vacancy (Vo) and Ag ions (Ag+) in the Ag/SnO2/p++-Si memristor can efficiently modulate the formation and abruption of conductive filaments, thereby resulting in a high on/off ratio (>106), long memory retention (10-year extrapolation), and low switching variability (SV = 6.85%). Multiple synaptic functions, such as paired-pulse facilitation, long-term potentiation/depression, and spike-time dependent plasticity, are demonstrated. Finally, facilitated by the symmetric analog weight updating and multiple conductance states, a high image recognition accuracy of ≥ 91.39% is achieved, substantiating its feasibility for analog in-memory computing. This study highlights the significance of synergistically modulating conductive filaments in optimizing performance trade-offs, balancing memory window, retention, and endurance, which demonstrates techniques for regulating ion migration, rendering them a promising approach for enabling cutting-edge neuromorphic applications.

Electrochemical random-access memory: recent advances in materials, devices, and systems towards neuromorphic computing.

Artificial neural networks (ANNs), inspired by the human brain's network of neurons and synapses, enable computing machines and systems to execute cognitive tasks, thus embodying artificial intelligence (AI). Since the performance of ANNs generally improves with the expansion of the network size, and also most of the computation time is spent for matrix operations, AI computation have been performed not only using the general-purpose central processing unit (CPU) but also architectures that facilitate parallel computation, such as graphic processing units (GPUs) and custom-designed application-specific integrated circuits (ASICs). Nevertheless, the substantial energy consumption stemming from frequent data transfers between processing units and memory has remained a persistent challenge. In response, a novel approach has emerged: an in-memory computing architecture harnessing analog memory elements. This innovation promises a notable advancement in energy efficiency. The core of this analog AI hardware accelerator lies in expansive arrays of non-volatile memory devices, known as resistive processing units (RPUs). These RPUs facilitate massively parallel matrix operations, leading to significant enhancements in both performance and energy efficiency. Electrochemical random-access memory (ECRAM), leveraging ion dynamics in secondary-ion battery materials, has emerged as a promising candidate for RPUs. ECRAM achieves over 1000 memory states through precise ion movement control, prompting early-stage research into material stacks such as mobile ion species and electrolyte materials. Crucially, the analog states in ECRAMs update symmetrically with pulse number (or voltage polarity), contributing to high network performance. Recent strides in device engineering in planar and three-dimensional structures and the understanding of ECRAM operation physics have marked significant progress in a short research period. This paper aims to review ECRAM material advancements through literature surveys, offering a systematic discussion on engineering assessments for ion control and a physical understanding of array-level demonstrations. Finally, the review outlines future directions for improvements, co-optimization, and multidisciplinary collaboration in circuits, algorithms, and applications to develop energy-efficient, next-generation AI hardware systems.

Recent Advances in In-Memory Computing: Exploring Memristor and Memtransistor Arrays with 2D Materials.

The conventional computing architecture faces substantial challenges, including high latency and energy consumption between memory and processing units. In response, in-memory computing has emerged as a promising alternative architecture, enabling computing operations within memory arrays to overcome these limitations. Memristive devices have gained significant attention as key components for in-memory computing due to their high-density arrays, rapid response times, and ability to emulate biological synapses. Among these devices, two-dimensional (2D) material-based memristor and memtransistor arrays have emerged as particularly promising candidates for next-generation in-memory computing, thanks to their exceptional performance driven by the unique properties of 2D materials, such as layered structures, mechanical flexibility, and the capability to form heterojunctions. This review delves into the state-of-the-art research on 2D material-based memristive arrays, encompassing critical aspects such as material selection, device performance metrics, array structures, and potential applications. Furthermore, it provides a comprehensive overview of the current challenges and limitations associated with these arrays, along with potential solutions. The primary objective of this review is to serve as a significant milestone in realizing next-generation in-memory computing utilizing 2D materials and bridge the gap from single-device characterization to array-level and system-level implementations of neuromorphic computing, leveraging the potential of 2D material-based memristive devices.

Content-Addressable Memories and Transformable Logic Circuits Based on Ferroelectric Reconfigurable Transistors for In-Memory Computing.

As a promising alternative to the von Neumann architecture, in-memory computing holds the promise of delivering a high computing capacity while consuming low power. In this paper, we show that the ferroelectric reconfigurable transistor can serve as a versatile logic-in-memory unit that can perform logic operations and data storage concurrently. When functioning as memory, a ferroelectric reconfigurable transistor can implement content-addressable memory (CAM) with a 1-transistor-per-bit density. With the switchable polarity of the ferroelectric reconfigurable transistor, XOR/XNOR-like matching operation in CAM is realized in a single transistor, which can offer a significant improvement in area and energy efficiency compared to conventional CAMs. NAND- and NOR-arrays of CAMs are also demonstrated, which enable multibit matching in a single reading operation. In addition, the NOR array of CAM cells effectively measures the Hamming distance between the input query and the stored entries. When functioning as a logic element, a ferroelectric reconfigurable transistor can be switched between n- and p-type modes. Utilizing the switchable polarity of these ferroelectric Schottky barrier transistors, we demonstrate reconfigurable logic gates with NAND/NOR dual functions, whose input-output mapping can be transformed in real time without changing the layout, and the configuration is nonvolatile.

Self-Rectifying Memristors for Three-Dimensional In-Memory Computing.

Costly data movement in terms of time and energy in traditional von Neumann systems is exacerbated by emerging information technologies related to artificial intelligence. In-memory computing (IMC) architecture aims to address this problem. Although the IMC hardware prototype represented by a memristor is developed rapidly and performs well, the sneak path issue is a critical and unavoidable challenge prevalent in large-scale and high-density crossbar arrays, particularly in three-dimensional (3D) integration. As a perfect solution to the sneak-path issue, a self-rectifying memristor (SRM) is proposed for 3D integration because of its superior integration density. To date, SRMs have performed well in terms of power consumption (aJ level) and scalability (>102  Mbit). Moreover, SRM-configured 3D integration is considered an ideal hardware platform for 3D IMC. This review focuses on the progress in SRMs and their applications in 3D memory, IMC, neuromorphic computing, and hardware security. The advantages, disadvantages, and optimization strategies of SRMs in diverse application scenarios are illustrated. Challenges posed by physical mechanisms, fabrication processes, and peripheral circuits, as well as potential solutions at the device and system levels, are also discussed.