A 10-Channel, 120 nW/Channel, Reconfigurable Capacitance-to-Digital Converter for Sub- µW Robust Wearable Sensing.

This paper presents a 10-channel, 120 nW/channel, reconfigurable capacitance-to-digital converter (CDC) enabling sub- µW wearable sensing applications. The proposed multi-channel architecture supports 10 channels with a shared reconfigurable 6-bit differential analog-to-digital converter (ADC). The reconfigurable nature of the CDC enables adaptive sensing range and sensing speed based on the target application. Furthermore, the architecture performs both on/off-chip parasitic correction and baseline calibration to measure the change in capacitance ( ∆C), excluding baseline and parasitic capacitances. The experimental results show the measurement range of ∆C are 5.34 pF for 1x sensitivity and 1.8 pF for 3x sensitivity respectively. The capacitive divider-based architecture excludes power-hungry operational trans-impedance amplifiers for capacitance to voltage conversion, and the architecture supports programmable channel access to activate or deactivate each channel independently. The random interrupt protection logic avoids any broken sample or data error in a sampling window. Additionally, the channel monitoring logic helps keep track of specific channel information. The measured silicon result shows a total power consumption of 1.2 µW for 1.6 kHz sampling frequency when driven by a 32 kHz clock, which is 8.6x less than prior works. The CDC is also tested with DMMP (dimethyl-methylphosphonate) gas sensor in gas chromatography (GC). Implemented in 65 nm CMOS process, the 10-channel CDC occupies 0.251 mm2 of active area (0.0251 mm2/Ch).

A Standard-Cell-Based Neuro-Inspired Integrate-and-Fire Analog-to-Time Converter for Biological and Low-Frequency Signals - Comparison With Analog Version.

Continuous-time asynchronous data converters namely, analog-to-digital converters and analog-to-time converters, can be beneficial for certain types of applications, such as, processing of biological signals with sparse information. A particular case of these converters is the integrate-and-fire converter (IFC) that is inspired by the neural system. If it is possible to develop a standard-cell-based (SCB) IFC circuit to perform well in advanced technology nodes, it will benefit from the simplicity of SCB circuit designs and can be implemented in widely available field-programmable gate arrays (FPGAs). This way, this paper proposes two IFC circuits designed and prototyped in a 130 nm CMOS standard process. The first is a novel SCB open-loop dynamic IFC. The latter, is a closed-loop analog IFC with conventional blocks. This paper presents a through comparison between the two IFC circuits. They have a power dissipation of 59 µW and 53 µW, and an energy per pulse of 18 pJ and 1060 pJ, SCB and analog IFC, respectively. The SCB IFC has one of the lowest energy per pulse consumption reported for IFC circuits. The analog IFC, being fully differential, is to our knowledge the first of its kind. Moreover, they do not require an external clock. They can convert signals with a peak-to-peak amplitude from 1.6 mV to 28 mV and 0.6 mV to 2.4 mV, and a frequency range of 2 Hz to 42 kHz and 10 Hz to 4 kHz, SCB and analog IFC, respectively. Presenting low normalized RMS conversion plus reconstruction errors, below 5.2%. The maximum pulse density (average firing-rate) is 3300 kHz, for the SCB and 50 kHz, for the analog IFC.

Intan Technologies integrated circuits can produce analog-to-digital conversion artifacts that affect neural signal acquisition.

Objective.Intan Technologies' integrated circuits (ICs) are valuable tools for neurophysiological data acquisition, providing signal amplification, filtering, and digitization from many channels (up to 64 channels/chip) at high sampling rates (up to 30 kSPS) within a compact package (⩽9× 7 mm). However, we found that the analog-to-digital converters (ADCs) in the Intan RHD2000 series ICs can produce artifacts in recorded signals. Here, we examine the effects of these ADC artifacts on neural signal quality and describe a method to detect them in recorded data.Approach.We identified two types of ADC artifacts produced by Intan ICs: 1) jumps, resulting from missing output codes, and 2) flatlines, resulting from overrepresented output codes. We identified ADC artifacts in neural recordings acquired with Intan RHD2000 ICs and tested the repeated performance of 17 ICsin vitro. With the on-chip digital-signal-processing disabled, we detected the ADC artifacts in each test recording by examining the distribution of unfiltered ADC output codes.Main Results.We found larger ADC artifacts in recordings using the Intan RHX data acquisition software versions 3.0-3.2, which did not run the necessary ADC calibration command when the inputs to the Intan recording controller were rescanned. This has been corrected in the Intan RHX software version 3.3. We found that the ADC calibration routine significantly reduced, but did not fully eliminate, the occurrence and size of ADC artifacts as compared with recordings acquired when the calibration routine was not run (p< 0.0001). When the ADC calibration routine was run, we found that the artifacts produced by each ADC were consistent over time, enabling us to sort ICs by performance.Significance.Our findings call attention to the importance of evaluating signal quality when acquiring electrophysiological data using Intan Technologies ICs and offer a method for detecting ADC artifacts in recorded data.

An Ultra-Low Power Fixed-Window Level Crossing ADC for ECG Recording.

In this paper, a novel fixed-window level-crossing analog-to-digital converter (LCADC) is proposed for the ECG monitoring application. The proposed circuit is implemented using fewer comparators and reference levels compared to the conventional structure, which results in a decrease in complexity and occupied silicon area. Also, the power consumption is reduced considerably by decreasing the activity of the comparator. Simulation results show a 5-fold reduction in activity by applying the standard ECG signals to the proposed structure. The proposed circuit is implemented in 0.18 µm CMOS technology using a 0.9 V supply voltage. Measurement results show a 5.9 nW power consumption and a 7.4-bit resolution. The circuit occupies a 0.05846 mm2 silicon area. A typical level-crossing-based R-peak-detection algorithm is applied to the output samples of the LCADC, which shows the effectiveness of using this type of sampling.

A Direct Current-Sensing VCO-Based 2nd-Order Continuous-Time Sigma-Delta Modulator for Biosensor Readout Applications.

A second-order voltage-controlled oscillator (VCO)-based continuous-time sigma-delta modulator (CTSDM) for current-sensing readout applications is proposed. Current signals from the sensor can directly be quantized by the proposed VCO-based CTSDM, which does not require any extra trans-impedance amplifiers. With the proportional-integral (PI) structure and a VCO phase integrator, the capability of second-order noise shaping is available to reduce the in-band quantization noise. The PI structure can be simply realized by a resistor in series with the integrating capacitor, which can reduce the architecture complexity and maintain the stability of the system. The current-steering digital-to-analog converter with tail and sink current sources is used on the feedback path for the subtraction of the current-type input signal. All the components of the circuit are scaling friendly and applicable to current-sensing readout applications in the Internet of Things (IoT). The proposed VCO-based CTSDM implemented in a 0.18-µm standard CMOS process has a measured signal-to-noise and distortion ratio (SNDR) of 74.6 dB at 10 kHz bandwidth and consumes 44.8 µw only under a supply voltage of 1.2 V, which can achieve a Figure-of-Merit (FoM) of 160.76 dB.

High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor.

The application requirements of high frame rate CMOS image sensors (CIS) in the industry have not been satisfied due to the speed limitations in traditional single-slope and serial two-step analog-to-digital converters (ADCs). In this paper, a high-speed fully differential two-step ADC design method for CIS was proposed. The proposed method was based on differential ramp and time-to-digital conversion (TDC) technology. A parallel conversion mode was formed that is different from serial conversion, and the robustness of the system was ensured due to the existence of differential ramps. Aiming at the inconsistency between traditional TDC technology and single-slope ADC, a TDC technology based on level coding was proposed. The proposed technology achieves the TDC in the last clock cycle of analog-to-digital conversion, and realized a two-step conversion process at another level. This paper presents a complete circuit design, layout design, and test verification of the proposed design method based on the 55 nm 1P4M CMOS experimental platform. Under the design environment of the analog voltage of 3.3 V, the digital voltage of 1.2 V, the clock frequency of 100 MHz, and a dynamic input range of 1.6 V, this design was a 12-bit ADC with a conversion time of 480 ns, column-level power consumption of 62 µW, differential nonlinearity (DNL) of +0.6/-0.6 LSB, and integral nonlinearity (INL) of +1.2/-1.4 LSB. Furthermore, it achieved a signal-to-noise distortion ratio (SNDR) of 70.08 dB. The proposed design provided a large area array with a high frame rate, and compared with the existing advanced single-slope ADC, its conversion speed increased by more than 52%. It provides an effective solution for the implementation of high frame frequency CIS.

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components.

A slope analog-to-digital converter (ADC) amenable to be fully implemented on a digital field programmable gate array (FPGA) without requiring any external active or passive components is proposed in this paper. The amplitude information, encoded in the transition times of a standard LVDS differential input-driven by the analog input and by the reference slope generated by an FPGA output buffer-is retrieved by an FPGA time-to-digital converter. Along with the ADC, a new online calibration algorithm is developed to mitigate the influence of process, voltage, and temperature variations on its performance. Measurements on an ADC prototype reveal an analog input range from 0.3 V to 1.5 V, a least significant bit (LSB) of 2.6 mV, and an effective number of bits (ENOB) of 7.4-bit at 600 MS/s. The differential nonlinearity (DNL) is in the range between -0.78 and 0.70 LSB, and the integral nonlinearity (INL) is in the range from -0.72 to 0.78 LSB.

Características de calidad digital de las revistas mexicanas calificadas en el Catálogo 2. 0 de Latindex / Digital quality characteristics of Mexican academic journals assessed in the Latindex Catalog 2. 0

Resumen Objetivo: identificar el grado de integración de características de calidad inherentes a las revistas digitales para valorar la forma en cómo están aprovechando las actuales herramientas que facilitan el acceso y uso de información científica. Metodología: se seleccionan las ocho características digitales de la metodología del Catálogo 2.0 de Latindex y se comprueba su presencia en los sitios web institucionales de 195 revistas académicas editadas en México. Resultados: Las características que presentan menor ocurrencia son los servicios de interactividad con las personas lectoras, el uso de más de un formato de edición para la consulta de los textos completos, así como el establecimiento de políticas de preservación digital, todas ellas con menos del 50% de cumplimiento. Del grupo estudiado, 127 revistas (65%) integraron entre cinco y ocho características en sus sitios web. Conclusiones: Se percibe que las revistas del estudio cumplen de manera diferente en la integración de los criterios de calidad digital; asimismo, se hace evidente que la mayoría no aprovechan a cabalidad las herramientas y servicios digitales disponibles en el gestor OJS, el cual es utilizado por casi la totalidad de las revistas analizadas. Se evidencia que aún hay trabajo por realizar para fomentar la integración de un mayor número de herramientas digitales, particularmente en las revistas que integran un mínimo de ellas y que sin embargo son denominadas digitales a la par de aquellas que presentan una mayor adaptación digital.

Abstract Objective: to identify the degree of integration of quality characteristics inherent to digital journals in order to assess how they are taking advantage of the current tools that facilitate the access and use of scientific information. Methodology: Eight digital characteristics of the Latindex Catalog 2.0 methodology were selected and their presence was verified in the institutional websites of 195 journals edited in Mexico. Results: Characteristics with a lesser degree of presence are: interactivity services with readers, use of more than one editing format for full text consultation, as well as the establishing of digital preservation policies, all of them with a compliance of less than 50%. Of the studied group, 127 journals (65%) integrated between five and eight characteristics on their websites. Conclusions: The integration of the eight quality criteria inherent to digital journals is differentially met by the studied publications. Likewise, it became clear that the digital tools and services available in the OJS manager are not being fully exploited by most of the analyzed journals. One of the most important findings is that there is necessary to promote the integration of a greater number of the characteristics specific to digital journals, particularly in those that remain in a very basic level and that nevertheless are referred as digital on par with other journals that have a higher digital adaptation.

Tendencias y desafíos en la creación de metadatos en proyectos de archivo de la web / Trends and challenges of metadata creation in web archiving projects

Resumen Este trabajo tiene como objetivo identificar prácticas y desafíos relacionados al manejo de metadatos en proyectos de archivado web. Se lleva a cabo un análisis de literatura sobre sobre metadatos en archivos de la web publicadas desde 2013, con particular atención a identificar estudios sobre estas prácticas en archivos y bibliotecas. Estos hallazgos apuntan a la necesidad de proveer una mayor contextualización sobre la conformación de un archivo o colección web, así como la importancia de tender puentes entre prácticas bibliotecológicas y archivísticas. Además, para profundizar sobre la importancia de los metadatos en proyectos de archivo de la web, se presenta como estudio de caso la conformación y catalogación de la Colección Web #RickyRenuncia, que forma parte del Proyecto RickyRenuncia, una iniciativa colaborativa y voluntaria para documentar las protestas que llevaron a la renuncia del gobernador de Puerto Rico en julio de 2019. A manera de conclusión, se argumenta sobre la necesidad de conocer más sobre prácticas de archivado web en Latinoamérica y el Caribe, y sobre la posibilidad de establecer redes de colaboración dirigidas a fortalecer la preservación de contenidos web en la región.

Abstract This paper aims to identify practices and challenges related to metadata management in web archiving projects. An analysis of literature on metadata in web archives published since 2013 is carried out, with particular attention to identify studies on these practices in archives and libraries. These findings point to the need to provide further contextualization on the shaping of a web archive or collection, as well as the importance of building bridges between library and archival practices. In addition, to deepen on the importance of metadata in web archiving projects, the conformation and cataloging of the #RickyRenuncia Web Collection, which is part of the RickyRenuncia Project, a collaborative and voluntary initiative to document the protests that led to the resignation of the governor of Puerto Rico in July 2019, is presented as a case study. By way of conclusion, it argues about the need to learn more about web archiving practices in Latin America and the Caribbean, and about the possibility of establishing collaborative networks aimed at strengthening the preservation of web content in the region.

A Wide Dynamic Range Sigma-Delta Modulator for EEG Acquisition Using Randomized DWA and Dynamic-Modulated Scaling-Down Techniques.

This paper proposes a wide dynamic range (DR) and high-resolution discrete-time (DT) 2-order 4-bit sigma-delta modulator with a novel dynamic-modulated scaling-down (DM-SD) technology for non-invasive electroencephalogram (EEG) acquisition. The DM-SD technology can expand the input dynamic range and suppress large input offsets at the same time. The modulator was designed with 180nm CMOS technology with an area of 0.49 mm2. We achieve a 118.1 dB SNDR when the input signal is 437.5 Hz and the signal bandwidth is 1500 Hz. Due to the proposed DM-SD technology, the DR is expanded to 126 dB. The power consumption of the whole modulator is 1.6 mW and a 177.8 dB Schreier figure-of-merit (FoMs) is realized.

Systematization and Comparison of the Binary Successive Approximation Variants.

This paper presents a systematization and a comparison of the binary successive approximation (SA) variants. Three different variants are distinguished and all of them are applied in the analog-to-digital conversion. Regardless of an analog-to-digital converter circuit solution, the adoption of the specific SA variant imposes a particular character of the conversion process and related parameters. One of them is the ability to direct conversion of non-removeable physical quantities such as time intervals. Referencing to this aspect a general systematization of the variants and a name for each of them is proposed. In addition, the article raises the issues related to the complexity of implementation and energy consumption for each of the discussed binary SA variants.

A pneumatic random-access memory for controlling soft robots.

Pneumatically-actuated soft robots have advantages over traditional rigid robots in many applications. In particular, their flexible bodies and gentle air-powered movements make them more suitable for use around humans and other objects that could be injured or damaged by traditional robots. However, existing systems for controlling soft robots currently require dedicated electromechanical hardware (usually solenoid valves) to maintain the actuation state (expanded or contracted) of each independent actuator. When combined with power, computation, and sensing components, this control hardware adds considerable cost, size, and power demands to the robot, thereby limiting the feasibility of soft robots in many important application areas. In this work, we introduce a pneumatic memory that uses air (not electricity) to set and maintain the states of large numbers of soft robotic actuators without dedicated electromechanical hardware. These pneumatic logic circuits use normally-closed microfluidic valves as transistor-like elements; this enables our circuits to support more complex computational functions than those built from normally-open valves. We demonstrate an eight-bit nonvolatile random-access pneumatic memory (RAM) that can maintain the states of multiple actuators, control both individual actuators and multiple actuators simultaneously using a pneumatic version of time division multiplexing (TDM), and set actuators to any intermediate position using a pneumatic version of analog-to-digital conversion. We perform proof-of-concept experimental testing of our pneumatic RAM by using it to control soft robotic hands playing individual notes, chords, and songs on a piano keyboard. By dramatically reducing the amount of hardware required to control multiple independent actuators in pneumatic soft robots, our pneumatic RAM can accelerate the spread of soft robotic technologies to a wide range of important application areas.

Power Efficiency Comparison of Event-Driven and Fixed-Rate Signal Conversion and Compression for Biomedical Applications.

Energy-constrained biomedical recording systems need power-efficient data converters and good signal compression in order to meet the stringent power consumption requirements of many applications. In literature today, typically a SAR ADC in combination with digital compression is used. Recently, alternative event-driven sampling techniques have been proposed that incorporate compression in the ADC, such as level-crossing A/D conversion. This paper describes the power efficiency analysis of such level-crossing ADC (LCADC) and the traditional fixed-rate SAR ADC with simple compression. A model for the power consumption of the LCADC is derived, which is then compared to the power consumption of the SAR ADC with zero-order hold (ZOH) compression for multiple biosignals (ECG, EMG, EEG, and EAP). The LCADC is more power efficient than the SAR ADC up to a cross-over point in quantizer resolution (for example 8 bits for an EEG signal). This cross-over point decreases with the ratio of the maximum to average slope in the signal of the application. It also changes with the technology and design techniques used. The LCADC is thus suited for low to medium resolution applications. In addition, the event-driven operation of an LCADC results in fewer data to be transmitted in a system application. The event-driven LCADC without timer and with single-bit quantizer achieves a reduction in power consumption at system level of two orders of magnitude, an order of magnitude better than the SAR ADC with ZOH compression. At system level, the LCADC thus offers a big advantage over the SAR ADC.

Cloud-based ECG monitoring using event-driven ECG acquisition and machine learning techniques.

An approach is proposed for the detection of chronic heart disorders from the electrocardiogram (ECG) signals. It utilizes an intelligent event-driven ECG signal acquisition system to achieve a real-time compression and effective signal processing and transmission. The experimental results show that grace of event-driven nature an overall 2.6 times compression and bandwidth utilization gain is attained by the suggested solution compared to the counter classical methods. It results in a significant reduction in the complexity and execution time of the post denoising, features extraction and classification processes. The overall system precision is studied in terms of the classification accuracy, the F-measure, the area under the ROC curve (AUC) and the Kappa statistics. The best classification accuracy of 94.07% is attained. It confirms that the designed event-driven solution realizes a computationally efficient automatic diagnosis of the cardiac arrhythmia while achieving a high precision decision support for cloud-based mobile health monitoring.

A 0.3V 10b 3MS/s SAR ADC With Comparator Calibration and Kickback Noise Reduction for Biomedical Applications.

This paper presents a 10-bit successive approximation analog-to-digital converter (ADC) that operates at an ultralow voltage of 0.3 V and can be applied to biomedical implants. The study proposes several techniques to improve the ADC performance. A pipeline comparator was utilized to maintain the advantages of dynamic comparators and reduce the kickback noise. Weight biasing calibration was used to correct the offset voltage without degrading the operating speed of the comparator. The incorporation of a unity-gain buffer improved the bootstrap switch leakage problem during the hold period and reduced the effect of parasitic capacitances on the digital-to-analog converter. The chip was fabricated using 90-nm CMOS technology. The data measured at a supply voltage of 0.3 V and sampling rate of 3 MSps for differential nonlinearity and integral nonlinearity were +0.83/-0.54 and +0.84/-0.89, respectively, and the signal-to-noise plus distortion ratio and effective number of bits were 56.42 dB and 9.08 b, respectively. The measured total power consumption was 6.6 µW at a figure of merit of 4.065 fJ/conv.-step.

Encoding multiple digital DNA signals in a single analog channel.

For many analytic and biomedical applications, the presence of an analyte above or below a critical concentration is more informative for decision making than the actual concentration value. Straightforward analog-to-digital signal conversion does not take full advantage of the precision and dynamic range of modern sensors. Here, we present and experimentally demonstrate an analog-to-multiple-digital signal conversion, reporting digital signals that indicate whether the concentrations of specific DNA sequences exceed respective threshold values. These threshold values can be individually programmed for each target sequence. Experimentally, we showed representation of four DNA targets' information in a single fluorescence channel.

A Wide Dynamic Range Neural Data Acquisition System With High-Precision Delta-Sigma ADC and On-Chip EC-PC Spike Processor.

A high-performance, wide dynamic range, fully-integrated neural interface is one key component for many advanced bidirectional neuromodulation technologies. In this paper, to complement the previously proposed frequency-shaping amplifier (FSA) and high-precision electrical microstimulator, we will present a proof-of-concept design of a neural data acquisition (DAQ) system that includes a 15-bit, low-power Delta-Sigma analog-to-digital converter (ADC) and a real-time spike processor based on one exponential component-polynomial component (EC-PC) algorithm. High-precision data conversion with low power consumption and small chip area is achieved by employing several techniques, such as opamp-sharing, multi-bit successive approximation (SAR) quantizer, two-step summation, and ultra-low distortion data weighted averaging (DWA). The on-chip EC-PC engine enables low latency, automatic detection, and extraction of spiking activities, thus supporting closed-loop control, real-time data compression and /or neural information decoding. The prototype chip was fabricated in a 0.13  µm CMOS process and verified in both bench-top and In-Vivo experiments. Bench-top measurement results indicate the designed ADC achieves a peak signal-to-noise and distortion ratio (SNDR) of 91.8 dB and a dynamic range of 93.0 dB over a 10 kHz bandwidth, where the total power consumption of the modulator is only 20  µW at 1.0 V supply, corresponding to a figure-of-merit (FOM) of 31.4fJ /conversion-step. In In-Vivo experiments, the proposed DAQ system has been demonstrated to obtain high-quality neural activities from a rat's motor cortex and also greatly reduce recovery time from system saturation due to electrical microstimulation.

The Rehapiano-Detecting, Measuring, and Analyzing Action Tremor Using Strain Gauges.

We have developed a device, the Rehapiano, for the fast and quantitative assessment of action tremor. It uses strain gauges to measure force exerted by individual fingers. This article verifies the device's capability to measure and monitor the development of upper limb tremor. The Rehapiano uses a precision, 24-bit, analog-to-digital converter and an Arduino microcomputer to transfer raw data via a USB interface to a computer for processing, database storage, and evaluation. First, our experiments validated the device by measuring simulated tremors with known frequencies. Second, we created a measurement protocol, which we used to measure and compare healthy patients and patients with Parkinson's disease. Finally, we evaluated the repeatability of a quantitative assessment. We verified our hypothesis that the Rehapiano is able to detect force changes, and our experimental results confirmed that our system is capable of measuring action tremor. The Rehapiano is also sensitive enough to enable the quantification of Parkinsonian tremors.

A 2.64- µW 71-dB SNDR Discrete-Time Signal-Folding Amplifier for Reducing ADC's Resolution Requirement in Wearable ECG Acquisition Systems.

This paper presents the design of a low-power discrete-time signal-folding amplifier intended for use in place of programmable-gain amplifiers (PGA) in electrocardiogram (ECG) acquisition systems. The amplifier provides a fixed high gain while preventing output signal saturation even with rail-to-rail inputs, thanks to the proposed discrete-time signal folding technique; the fixed gain eliminates the need of gain-control circuitry while the high gain helps relax the resolution requirement of the analog-to-digital converter (ADC) that follows, thus resulting in lower power consumption and design complexity for the ADC. Fabricated in a standard 0.18- µm CMOS process, the amplifier occupies an active area of 0.254 mm2 and consumes 2.64  µW from a 1.2-V supply voltage. While amplifying a rail-to-rail input (2.4 Vpp differential) with a gain of 17.8 V/V, the amplifier achieves a signal-to-noise-plus-distortion ratio (SNDR) of 71 dB, thus making it very attractive for high-fidelity ECG recording amid large input interferences.

A Power and Area Efficient CMOS Stochastic Neuron for Neural Networks Employing Resistive Crossbar Array.

A power and area efficient CMOS stochastic neuron for resistive computing device-based neural networks is presented. The stochastic neuron performs both quantization and activation function simultaneously by using a single dynamic comparator and allows power-hungry analog to digital and digital to analog converters to be removed at the cost of the increased computation time. A network learning method utilizing a noisy sigmoid function is also presented to minimize the computation time with little accuracy degradation. A prototype neuron chip fabricated in 0.18µm CMOS process successfully demonstrates the neuron's performance and the learning method is verified through network simulations.