Significant improvement of n-contact performance and wall plug efficiency of AlGaN-based deep ultraviolet light-emitting diodes by atomic layer etching.

The reactive ion etching (RIE) process is needed to fabricate deep ultraviolet (DUV) light-emitting diodes (LEDs). However, the n-contact performance deteriorates when the high-Al n-AlGaN surface undergoes RIE, leading to decreased LED performance. In this study, we employed an atomic layer etching (ALE) technology to eliminate surface damage generated during the mesa etching process, thus enhancing the n-Al0.65Ga0.35N ohmic contact. The improved contact performance reduced LED operation voltage and mitigated device heat generation. It was observed that DUV LEDs treated with 200 cycles of ALE showed a reduction in operating voltage from 8.3 to 5.2 V at 10 mA, with a knee voltage of 4.95 V. The peak wall plug efficiency (WPE) was approximately 1.74 times that of reference devices. The x-ray photoelectron spectroscopy (XPS) analysis revealed that ALE removed the surface damage layer induced by plasma etching, eliminating surface nitrogen vacancies and increasing surface electron concentration. Consequently, it facilitated better ohmic contact formation on n-Al0.65Ga0.35N. This study demonstrates that the ALE technology achieves etching with minor surface damage and is suitable for use in III-nitride materials and devices to remove surface defects and contaminations, leading to improved device performance.

UV-assisted nanoimprint lithography: the impact of the loading effect in silicon on nanoscale patterns of metalens.

This work studies the impact of the silicon (Si) loading effect induced by deep reactive ion etching (DRIE) of silicon master molds on the UV-nanoimprint lithography (NIL) patterning of nanofeatures. The silicon molds were patterned with metasurface features with widths varying from 270 to 60 nm. This effect was studied by focus ion beam scanning electron microscopy (FIB-SEM) and atomic force microscopy (AFM). The Si loading etching effect is characterized by the variation of pattern feature depth concerning feature sizes because smaller features tend to etch more slowly than larger ones due to etchants being more difficult to pass through the smaller hole and byproducts being harder to diffuse out too. Thus, the NIL results obtained from the Si master mold contain different pattern geometries concerning pattern quality and residual photoresist layer thickness. The obtained results are pivotal for NIL for fabricating devices with various geometrical nanostructures as the research field moves towards commercial applications.

Etching-free pixel definition in InGaN green micro-LEDs.

The traditional plasma etching process for defining micro-LED pixels could lead to significant sidewall damage. Defects near sidewall regions act as non-radiative recombination centers and paths for current leakage, significantly deteriorating device performance. In this study, we demonstrated a novel selective thermal oxidation (STO) method that allowed pixel definition without undergoing plasma damage and subsequent dielectric passivation. Thermal annealing in ambient air oxidized and reshaped the LED structure, such as p-layers and InGaN/GaN multiple quantum wells. Simultaneously, the pixel areas beneath the pre-deposited SiO2 layer were selectively and effectively protected. It was demonstrated that prolonged thermal annealing time enhanced the insulating properties of the oxide, significantly reducing LED leakage current. Furthermore, applying a thicker SiO2 protective layer minimized device resistance and boosted device efficiency effectively. Utilizing the STO method, InGaN green micro-LED arrays with 50-, 30-, and 10-µm pixel sizes were manufactured and characterized. The results indicated that after 4 h of air annealing and with a 3.5-µm SiO2 protective layer, the 10-µm pixel array exhibited leakage currents density 1.2 × 10-6 A/cm2 at -10 V voltage and a peak on-wafer external quantum efficiency of ~6.48%. This work suggests that the STO method could become an effective approach for future micro-LED manufacturing to mitigate adverse LED efficiency size effects due to the plasma etching and improve device efficiency. Micro-LEDs fabricated through the STO method can be applied to micro-displays, visible light communication, and optical interconnect-based memories. Almost planar pixel geometry will provide more possibilities for the monolithic integration of driving circuits with micro-LEDs. Moreover, the STO method is not limited to micro-LED fabrication and can be extended to design other III-nitride devices, such as photodetectors, laser diodes, high-electron-mobility transistors, and Schottky barrier diodes.