Van der Waals polarity-engineered 3D integration of 2D complementary logic.

Vertical three-dimensional integration of two-dimensional (2D) semiconductors holds great promise, as it offers the possibility to scale up logic layers in the z axis1-3. Indeed, vertical complementary field-effect transistors (CFETs) built with such mixed-dimensional heterostructures4,5, as well as hetero-2D layers with different carrier types6-8, have been demonstrated recently. However, so far, the lack of a controllable doping scheme (especially p-doped WSe2 (refs. 9-17) and MoS2 (refs. 11,18-28)) in 2D semiconductors, preferably in a stable and non-destructive manner, has greatly impeded the bottom-up scaling of complementary logic circuitries. Here we show that, by bringing transition metal dichalcogenides, such as MoS2, atop a van der Waals (vdW) antiferromagnetic insulator chromium oxychloride (CrOCl), the carrier polarity in MoS2 can be readily reconfigured from n- to p-type via strong vdW interfacial coupling. The consequential band alignment yields transistors with room-temperature hole mobilities up to approximately 425 cm2 V-1 s-1, on/off ratios reaching 106 and air-stable performance for over one year. Based on this approach, vertically constructed complementary logic, including inverters with 6 vdW layers, NANDs with 14 vdW layers and SRAMs with 14 vdW layers, are further demonstrated. Our findings of polarity-engineered p- and n-type 2D semiconductor channels with and without vdW intercalation are robust and universal to various materials and thus may throw light on future three-dimensional vertically integrated circuits based on 2D logic gates.

A 30-m annual corn residue coverage dataset from 2013 to 2021 in Northeast China.

Crop residue cover plays a key role in the protection of black soil by covering the soil in the non-growing season against wind erosion and chopping for returning to the soil to increase organic matter in the future. Although there are some studies that have mapped the crop residue coverage by remote sensing technique, the results are mainly on a small scale, limiting the generalizability of the results. In this study, we present a novel corn residue coverage (CRC) dataset for Northeast China spanning the years 2013-2021. The aim of our dataset is to provide a basis to describe and monitor CRC for black soil protection. The accuracy of our estimation results was validated against previous studies and measured data, demonstrating high accuracy with a coefficient of determination (R2) of 0.7304 and root mean square error (RMSE) of 0.1247 between estimated and measured CRC in field campaigns. In addition, it is the first of its kind to offer the longest time series, enhancing its significance in long-term monitoring and analysis.

Flash-Based Computing-in-Memory Architecture to Implement High-Precision Sparse Coding.

To address the concerns with power consumption and processing efficiency in big-size data processing, sparse coding in computing-in-memory (CIM) architectures is gaining much more attention. Here, a novel Flash-based CIM architecture is proposed to implement large-scale sparse coding, wherein various matrix weight training algorithms are verified. Then, with further optimizations of mapping methods and initialization conditions, the variation-sensitive training (VST) algorithm is designed to enhance the processing efficiency and accuracy of the applications of image reconstructions. Based on the comprehensive characterizations observed when considering the impacts of array variations, the experiment demonstrated that the trained dictionary could successfully reconstruct the images in a 55 nm flash memory array based on the proposed architecture, irrespective of current variations. The results indicate the feasibility of using Flash-based CIM architectures to implement high-precision sparse coding in a wide range of applications.

Sub-10 nm HfZrO ferroelectric synapse with multiple layers and different ratios for neuromorphic computing.

To break the von Neumann bottleneck, emerging non-volatile memories have gained extensive attention in hardware implementing neuromorphic computing. The device scaling with low operating voltage is of great importance for delivering a high-integrating and energy-efficient neuromorphic system. In this paper, we fabricated sub-10 nm ferroelectric capacitors based on HfZrO (HZO) film with varying HfO and ZrO components. Compared to the conventional HZO capacitors (a constant component of 1:1), the varying component ferroelectric capacitors show similar remnant polarization but a lower coercive electric field (Ec). This enables the partial domain switching processed at a lower pulse amplitude and width, which is essential for emulating typical synaptic features. In the MNIST recognition task, the accuracy of sub-10 nm ferroelectric artificial synapse can approach ∼85.83%. Our findings may provide great potential for developing next-generation neuromorphic computing-based ultra-scaled ferroelectric artificial synapses.

A Novel Method to Analyze the Relationship between Thermoelectric Coefficient and Energy Disorder of Any Density of States in an Organic Semiconductor.

In this work, a unified method is proposed for analyzing the relationship between the Seebeck coefficient and the energy disorder of organic semiconductors at any multi-parameter density of states (DOS) to study carrier transport in disordered thermoelectric organic semiconductors and the physical meaning of improved DOS parameters. By introducing the Gibbs entropy, a new multi-parameter DOS and traditional Gaussian DOS are used to verify this method, and the simulated result of this method can well fit the experiment data obtained on three organic devices. In particular, the impact of DOS parameters on the Gibbs entropy can also influence the impact of the energy disorder on the Seebeck coefficient.

A Novel Density of States (DOS) for Disordered Organic Semiconductors.

In this work, we proposed a novel theory of DOS for disordered organic semiconductors based on the frontier orbital theory and probability statistics. The proposed DOS has been verified by comparing with other DOS alternatives and experimental data, and the mobility calculated by the proposed DOS is closer to experimental data than traditional DOS. Moreover, we also provide a detailed method to choose the DOS parameter for better use of the proposed DOS. This paper also contains a prediction for the DOS parameters, and it has been verified by the experimental data. More importantly, the physical meaning of the proposed DOS parameter has been explained by equilibrium energy theory and transport energy theory to make this proposed model more rational. Compared with the improved DOS based on Gaussian and exponential DOS, this work is a new attempt to combine probabilistic theory with physical theory related to DOS in disordered organic semiconductors, showing great significance for the further investigation of the properties of DOS.

An Efficient and Robust Partial Differential Equation Solver by Flash-Based Computing in Memory.

Flash memory-based computing-in-memory (CIM) architectures have gained popularity due to their remarkable performance in various computation tasks of data processing, including machine learning, neuron networks, and scientific calculations. Especially in the partial differential equation (PDE) solver that has been widely utilized in scientific calculations, high accuracy, processing speed, and low power consumption are the key requirements. This work proposes a novel flash memory-based PDE solver to implement PDE with high accuracy, low power consumption, and fast iterative convergence. Moreover, considering the increasing current noise in nanoscale devices, we investigate the robustness against the noise in the proposed PDE solver. The results show that the noise tolerance limit of the solver can reach more than five times that of the conventional Jacobi CIM solver. Overall, the proposed flash memory-based PDE solver offers a promising solution for scientific calculations that require high accuracy, low power consumption, and good noise immunity, which could help to develop flash-based general computing.

A Gate Programmable van der Waals Metal-Ferroelectric-Semiconductor Vertical Heterojunction Memory.

Ferroelectricity, one of the keys to realize non-volatile memories owing to the remanent electric polarization, is an emerging phenomenon in the 2D limit. Yet the demonstrations of van der Waals (vdW) memories using 2D ferroelectric materials as an ingredient are very limited. Especially, gate-tunable ferroelectric vdW memristive device, which holds promises in future multi-bit data storage applications, remains challenging. Here, a gate-programmable multi-state memory is shown by vertically assembling graphite, CuInP2 S6 , and MoS2 layers into a metal(M)-ferroelectric(FE)-semiconductor(S) architecture. The resulted devices seamlessly integrate the functionality of both FE-memristor (with ON-OFF ratios exceeding 105 and long-term retention) and metal-oxide-semiconductor field effect transistor (MOS-FET). Thus, it yields a prototype of gate tunable giant electroresistance with multi-levelled ON-states in the FE-memristor in the vertical vdW assembly. First-principles calculations further reveal that such behaviors originate from the specific band alignment between the FE-S interface. Our findings pave the way for the engineering of ferroelectricity-mediated memories in future implementations of 2D nanoelectronics.

Ferroelectricity induced double-direction conductance modulation in HfxZr1-xO2capacitors.

The artificial synapses are basic units in the hardware implementation of neuromorphic computing, whose performances should be gradually modulated under external stimuli. The underlying mechanism of the increasing and decreasing device conductance is still unclear in the Hf0.5Zr0.5O2based synapses. In this study, the Hf0.5Zr0.5O2capacitors with different stack orders are fabricated in atomic layer deposition, whose ferroelectric properties are investigated by analyzing the capacitance-voltage and polarization-voltage curves. The enhanced ferroelectricity is found after the rapid thermal annealing treatment for all the TiN/Hf0.5Zr0.5O2/TiN, TiN/HfO2-ZrO2/TiN and TiN/ZrO2-HfO2/TiN devices. In the device with poor ferroelectricity, the conductance gradually decreases under both positive and negative identical pulse schemes, which corresponds to the gradual dissolution process of the conductive filaments established in the initial pulse. For the capacitors with strong ferroelectricity, dual-direction conductance modulation can be observed due to the partial domain switching process, which can emulate the potentiation and depression process of biological synapses.

Defects Induced Charge Trapping/Detrapping and Hysteresis Phenomenon in MoS2 Field-Effect Transistors: Mechanism Revealed by Anharmonic Marcus Charge Transfer Theory.

One critical problem inhibiting the application of MoS2 field-effect transistors (FETs) is the hysteresis in their transfer characteristics, which is typically associated with charge trapping (CT) and charge detrapping (CDT) induced by atomic defects at the MoS2-dielectric interface. Here, we propose a novel atomistic framework to simulate electronic processes across the MoS2-SiO2 interface, demonstrating the distinct CT/CDT behavior of different types of atomic defects and further revealing the defect type(s) that most likely cause hysteresis. An anharmonic approximation of the classical Marcus theory is developed and combined with state-of-the-art density functional theory to calculate the gate bias-dependent CT/CDT rates. All the key electronic quantities are calculated with Heyd-Scuseria-Ernzerhof hybrid functionals. The results show that single Si-dangling bond defects are active electron trapping centers. Single O-dangling bond defects are active hole trapping centers, which are more likely to be responsible for the hysteresis phenomenon due to their significant CT rate and apparent threshold voltage shift. In contrast, double Si-dangling bond defects are not active trap centers. These findings provide fundamental physical insights for understanding the hysteresis behavior of MoS2 FETs and provide vital support for understanding and solving the reliability of nanoscale devices.

Temperature Impacts on Endurance and Read Disturbs in Charge-Trap 3D NAND Flash Memories.

Temperature effects should be well considered when designing flash-based memory systems, because they are a fundamental factor that affect both the performance and the reliability of NAND flash memories. In this work, aiming to comprehensively understanding the temperature effects on 3D NAND flash memory, triple-level-cell (TLC) mode charge-trap (CT) 3D NAND flash memory chips were characterized systematically in a wide temperature range (-30~70 °C), by focusing on the raw bit error rate (RBER) degradation during program/erase (P/E) cycling (endurance) and frequent reading (read disturb). It was observed that (1) the program time showed strong dependences on the temperature and P/E cycles, which could be well fitted by the proposed temperature-dependent cycling program time (TCPT) model; (2) RBER could be suppressed at higher temperatures, while its degradation weakly depended on the temperature, indicating that high-temperature operations would not accelerate the memory cells' degradation; (3) read disturbs were much more serious at low temperatures, while it helped to recover a part of RBER at high temperatures.

Digital and analog functionality in monolayer AlOx-based memristors with various oxidizer sources.

Memristors with the outstanding advantages are beneficial for neuromorphic computing and next-generation storage. Realizing various resistive switching behaviors in monolayer memristors is essential for understanding the device physics and fabricating fully memristive devices. In this paper, a simple and feasible method was proposed to achieve the digital and analog resistive switching in Cu/AlOx/Ag memristors by using ozone and water precursors in atomic layer deposition. According to the characterization results of surface topography, Raman spectrum and electrical measurement, the transition between the abrupt and gradual resistive switching was ascribed to the migration and diffusion of active electrode metal ions in the sparser, rougher and more amorphous AlOx dielectric films. The key features of biological synapses including long-term potentiation/depression, paired-pulse facilitation and learning-experience behaviors were emulated in the analog monolayer memristors. This study makes an important step towards the development of the sophisticated, multi-functional, and large-scale integrated neuromorphic devices and systems.

A tied Fermi liquid to Luttinger liquid model for nonlinear transport in conducting polymers.

Organic conjugated polymers demonstrate great potential in transistors, solar cells and light-emitting diodes, whose performances are fundamentally governed by charge transport. However, the morphology-property relationships and the underpinning charge transport mechanisms remain unclear. Particularly, whether the nonlinear charge transport in conducting polymers is appropriately formulated within non-Fermi liquids is not clear. In this work, via varying crystalline degrees of samples, we carry out systematic investigations on the charge transport nonlinearity in conducting polymers. Possible charge carriers' dimensionality is discussed when varying the molecular chain's crystalline orders. A heterogeneous-resistive-network (HRN) model is proposed based on the tied-link between Fermi liquids (FL) and Luttinger liquids (LL), related to the high-ordered crystalline zones and weak-coupled amorphous regions, respectively. The HRN model is supported by precise electrical and microstructural characterizations, together with theoretic evaluations, which well describes the nonlinear transport behaviors and provides new insights into the microstructure-correlated charge transport in organic solids.

Possible Luttinger liquid behavior of edge transport in monolayer transition metal dichalcogenide crystals.

In atomically-thin two-dimensional (2D) semiconductors, the nonuniformity in current flow due to its edge states may alter and even dictate the charge transport properties of the entire device. However, the influence of the edge states on electrical transport in 2D materials has not been sufficiently explored to date. Here, we systematically quantify the edge state contribution to electrical transport in monolayer MoS2/WSe2 field-effect transistors, revealing that the charge transport at low temperature is dominated by the edge conduction with the nonlinear behavior. The metallic edge states are revealed by scanning probe microscopy, scanning Kelvin probe force microscopy and first-principle calculations. Further analyses demonstrate that the edge-state dominated nonlinear transport shows a universal power-law scaling relationship with both temperature and bias voltage, which can be well explained by the 1D Luttinger liquid theory. These findings demonstrate the Luttinger liquid behavior in 2D materials and offer important insights into designing 2D electronics.

Improving Performances of In-Plane Transition-Metal Dichalcogenide Schottky Barrier Field-Effect Transistors.

Monolayer Schottky barrier (SB) field-effect transistors based on the in-plane heterojunction of 1T/1T'-phase (metallic) and 2H-phase (semiconducting) transition-metal dichalcogenides (TMDs) have been proposed following the recent experimental synthesis of such devices. By using density functional theory and ab initio simulations, intrinsic device performance, sub-10 nm scaling, and performance boosting of MoSe2, MoTe2, WSe2, and WTe2, SB field-effect transistors are systematically investigated. We find that the Schottky barrier heights (SBHs) of these in-plane 1T(1T')/2H contacts are proportional to their band gaps: the bigger band gap corresponds to bigger SBH. For four TMDs, the SBH of 1T/2H contact is always smaller than that of 1T'/2H contact. The WTe2 SB field-effect transistor can provide the best performance and satisfy the requirement of the high-performance transistor outlined by the International Technology Roadmap for Semiconductors down to a 6 nm gate length. In addition, the replacement of suitable 1T-TMD on the source/drain regions can modulate conduction band SB, leading to the 8.8 nm WSe2 SB field-effect transistor also satisfying the requirement. Moreover, the introduction of the underlap can increase the effective channel length and reduce the coupling between the source/drain and the channel, leading to the 5.1 nm WTe2 SB field-effect transistor also satisfying the International Technology Roadmap for Semiconductors high-performance requirement. The underlying physical mechanisms are discussed, and it is concluded that the in-plane SB engineering is the key point to optimize such two-dimensional devices.

Enhancement of tunneling current in phosphorene tunnel field effect transistors by surface defects.

The effects of the staggered double vacancies, hydrogen (H), 3d transition metals, for example cobalt, and semiconductor covalent atoms, for example, germanium, nitrogen, phosphorus (P) and silicon adsorption on the transport properties of monolayer phosphorene were studied using density functional theory and non-equilibrium Green's function formalism. It was observed that the performance of the phosphorene tunnel field effect transistors (TFETs) with an 8.8 nm scaling channel length could be improved most effectively, if the adatoms or vacancies were introduced at the source channel interface. For H and P doped devices, the upper limit of on-state currents of phosphorene TFETs were able to be quickly increased to 2465 µA µm-1 and 1652 µA µm-1, respectively, which not only outperformed the pristine sample, but also met the requirements for high performance logic applications for the next decade in the International Technology Roadmap for Semiconductors (ITRS). It was proved that the defect-induced band gap states make the effective tunneling path between the conduction band (CB) and valence band (VB) much shorter, so that the carriers can be injected easily from the left electrode, then transfer to the channel. In this regard, the tunneling properties of phosphorene TFETs can be manipulated using surface defects. In addition, the effects of spin polarization on the transport properties of doped phosphorene TFETs were also rigorously considered, H and P doped TFETs could achieve a high ON current of 1795 µA µm-1 and 1368 µA µm-1, respectively, which is closer to realistic nanodevices.