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1.
Opt Express ; 15(8): 5043-9, 2007 Apr 16.
Article in English | MEDLINE | ID: mdl-19532753

ABSTRACT

We demonstrate a novel scheme for 2R burst mode reception capable of operating error-free with 40 Gb/s variable length, asynchronous optical data packets that exhibit up to 9 dB packet-to-packet power variation. It consists of a single, hybrid integrated, SOA-based Mach-Zehnder Interferometer (SOA-MZI) with unequal splitting ratio couplers, configured to operate as a self-switch. We analyze theoretically the power equalization properties of unequal splitting ratio SOA-MZI switches and show good agreement between theory and experiment.

2.
Opt Express ; 15(16): 9948-53, 2007 Aug 06.
Article in English | MEDLINE | ID: mdl-19547344

ABSTRACT

We demonstrate an optical clock recovery circuit that extracts the line rate component on a per packet basis from short data packets at 40Gb/s. The circuit comprises a Fabry-Perot filter followed by a novel power limiting configuration, which in turn consists of a 5m highly nonlinear bismuth oxide fiber in cascade with an optical bandpass filter. Both experimental and simulation-based results are in close agreement and reveal that the proposed circuit acquires the timing information within only a small number of bits, yielding a packet clock for every respective data packet. Moreover, we investigate theoretically the scaling laws for the parameters of the circuit for operation beyond 40 Gb/s and present simulation results showing successful packet clock extraction for 160 Gb/s data packets. Finally, the circuit's potential for operation at 320 Gb/s is discussed, indicating that ultrafast packet clock recovery should be in principle feasible by exploiting the passive structure of the device and the fsec-scale nonlinear response of the optical fiber.

3.
Opt Express ; 14(26): 12665-9, 2006 Dec 25.
Article in English | MEDLINE | ID: mdl-19532158

ABSTRACT

We demonstrate an all-optical, self-synchronization scheme for optical packet switched network nodes. It provides both the packet clock signal and the packet beginning, marker pulse. The circuit uses two hybridly integrated MZI switches and has been evaluated with synchronous, asynchronous and variable length, data packets at 10 Gb/s. It is compact and requires relatively low energies to operate.

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