222Radon reduction in small-scale water supply systems using low-technology reduction methods in the Republic of Korea: A field research and mass balance model approach.

In rural areas, low-technology radon reduction methods are essential for safe access to clean groundwater. This study monitored the radon reduction rates in small-scale groundwater-based water supply systems in the Republic of Korea and also presented a mass balance equation using physical environmental conditions from three radon reduction methods. The mass balance results showed that the radon reduction rate would be affected by the groundwater flow rate (m3/day), capacity of the drainage facility (m3), surface area of air-water interface (m2), air-water ratio (dimensionless), and ventilation system. The radon reduction order was as follows: simultaneously powered and non-powered aeration method (free-fall (60.0 %) > aeration (19.6 %) > decay (0.9 %) > diffusion (0.2 %)), low-technology non-powered aeration (free-fall (60.0 %) > decay (3.4 %) > diffusion (0.9 %)), and only storage (free-fall (35.5 %) > decay (4.4 %) > diffusion (1.1 %)). Overall, non-powered aeration using the maximum free-fall effect has the potential for use as a low-technology reduction method and natural decay during water storage is the most important factor underlying seasonal variations in the reduction effect.

A Unified Current-Voltage Model for Metal Oxide-Based Resistive Random-Access Memory.

Resistive random-access memory (RRAM) is essential for developing neuromorphic devices, and it is still a competitive candidate for future memory devices. In this paper, a unified model is proposed to describe the entire electrical characteristics of RRAM devices, which exhibit two different resistive switching phenomena. To enhance the performance of the model by reflecting the physical properties such as the length index of the undoped area during the switching operation, the Voltage ThrEshold Adaptive Memristor (VTEAM) model and the tungsten-based model are combined to represent two different resistive switching phenomena. The accuracy of the I-V relationship curve tails of the device is improved significantly by adjusting the ranges of unified internal state variables. Furthermore, the unified model describes a variety of electrical characteristics and yields continuous results by using the device's current-voltage relationship without dividing its fitting conditions. The unified model describes the optimized electrical characteristics that reflect the electrical behavior of the device.

Circuit Optimization Method to Reduce Disturbances in Poly-Si 1T-DRAM.

A capacitorless one-transistor dynamic random-access memory device (1T-DRAM) is proposed to resolve the scaling problem in conventional one-transistor one-capacitor random-access memory (1T-1C-DRAM). Most studies on 1T-DRAM focus on device-level operation to replace 1T-1C-DRAM. To utilize 1T-DRAM as a memory device, we must understand its circuit-level operation, in addition to its device-level operation. Therefore, we studied the memory performance depending on device location in an array circuit and the circuit configuration by using the 1T-DRAM structure reported in the literature. The simulation results show various disturbances and their effects on memory performance. These disturbances occurred because the voltages applied to each device during circuit operation are different. We analyzed the voltage that should be applied to each voltage line in the circuit to minimize device disturbance and determine the optimized bias condition and circuit structure to achieve a large sensing margin and realize operation as a memory device. The results indicate that the memory performance improves when the circuit has a source line and the bias conditions of the devices differ depending on the write data at the selected device cell. Therefore, the sensing margin of the 1T-DRAM used herein can expectedly be improved by applying the proposed source line (SL) structure.

New Simulation Method for Dependency of Device Degradation on Bending Direction and Channel Length.

The dependency of device degradation on bending direction and channel length is analyzed in terms of bandgap states in amorphous indium-gallium-zinc-oxide (a-IGZO) films. The strain distribution in an a-IGZO film under perpendicular and parallel bending of a device with various channel lengths is investigated by conducting a three-dimensional mechanical simulation. Based on the obtained strain distribution, new device simulation structures are suggested in which the active layer is defined as consisting of multiple regions. The different arrangements of a highly strained region and density of states is proportional to the strain account for the measurement tendency. The analysis performed using the proposed structures reveals the causes underlying the effects of different bending directions and channel lengths, which cannot be explained using the existing simulation methods in which the active layer is defined as a single region.

Analysis of Grain Boundary Dependent Memory Characteristics in Poly-Si One-Transistor Dynamic Random-Access Memory.

A capacitorless one-transistor dynamic random-access memory cell with a polysilicon body (poly-Si 1T-DRAM) has a cost-effective fabrication process and allows a three-dimensional stacked architecture that increases the integration density of memory cells. Also, since this device uses grain boundaries (GBs) as a storage region, it can be operated as a memory cell even in a thin body device. GBs are important to the memory characteristics of poly-Si 1T-DRAM because the amount of trapped charge in the GBs determines the memory's data state. In this paper, we report on a statistical analysis of the memory characteristics of poly-Si 1T-DRAM cells according to the number and location of GBs using TCAD simulation. As the number of GBs increases, the sensing margin and retention time of memory cells deteriorate due to increasing trapped electron charge. Also, "0" state current increases and memory performance degrades in cells where all GBs are adjacent to the source or drain junction side in a strong electric field. These results mean that in poly-Si 1T-DRAM design, the number and location of GBs in a channel should be considered for optimal memory performance.

Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM.

A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). A poly-Si 1T-DRAM cell operates as a memory by utilizing the charge trapped at the grain boundaries (GBs) of its poly-Si body; vertical GBs are formed randomly during fabrication. This paper describes technology computer aided design (TCAD) device simulations performed to investigate the sensing margin and retention time of poly-Si 1T-DRAM as a function of its lateral GB location. The results show that the memory's operating mechanism changes with the GB's lateral location because of a corresponding change in the number of trapped electrons or holes. We determined the optimum lateral GB location for the best memory performance by considering both the sensing margin and retention time. We also performed simulations to analyze the effect of a lateral GB on the operation of a poly-Si 1T-DRAM that has a vertical GB. The memory performance of devices without a lateral GB significantly deteriorates when a vertical GB is located near the source or drain junction, while devices with a lateral GB have little change in memory characteristics with different vertical GB locations. This means that poly-Si 1T-DRAM devices with a lateral GB can operate reliably without any memory performance degradation from randomly determined vertical GB locations.

Effect of Initial Synaptic State on Pattern Classification Accuracy of 3D Vertical Resistive Random Access Memory (VRRAM) Synapses.

Amidst the considerable attention artificial intelligence (AI) has attracted in recent years, a neuromorphic chip that mimics the biological neuron has emerged as a promising technology. Memristor or Resistive random-access memory (RRAM) is widely used to implement a synaptic device. Recently, 3D vertical RRAM (VRRAM) has become a promising candidate to reducing resistive memory bit cost. This study investigates the operation principle of synapse in 3D VRRAM architecture. In these devices, the classification response current through a vertical pillar is set by applying a training algorithm to the memristors. The accuracy of neural networks with 3D VRRAM synapses was verified by using the HSPICE simulator to classify the alphabet in 7×7 character images. This simulation demonstrated that 3D VRRAMs are usable as synapses in a neural network system and that a 3D VRRAM synapse should be designed to consider the initial value of the memristor to prepare the training conditions for high classification accuracy. These results mean that a synaptic circuit using 3D VRRAM will become a key technology for implementing neural computing hardware.

Analysis of Organic Light-Emitting Diode SPICE Models with Constant or Voltage-Dependent Components.

A simplified OLED SPICE model with two resistors and two capacitors that have constant or voltagedependent (VD) values is proposed. Our model includes physical characteristics such as voltage and frequency dependency and agrees well with measurements. In this paper, we analyze the OLED frequency dependency effects and RC delay properties by controlling model parameters for DC, AC, and transient conditions. Importantly, we found that a model with constant parameters is simple and is accurate enough. Based on our simulation results, we suggest a new guideline for an OLED SPICE circuit model and simulation target.

Charge Based Current-Voltage Model for the Silicon on Insulator Junctionless Field-Effect Transistor.

In this study, we propose an accurate and simple current-voltage model for an SOI-JLFET based on a solution of the Poisson equation. The model is divided into three regions: accumulation, accumulation-depletion, and depletion. The charge density in each region is calculated with the Poisson equation and region-specific boundary conditions, and then the current is obtained by integrating the charge density with consideration of the Vds effect. The proposed model, which was implemented in HSPICE using Verilog-A, was validated using TCAD simulation for various physical conditions such as SOI channel thickness, gate oxide thickness, and channel doping concentration type. According to simulation results by the error rate calculation, our model shows more than 90% accuracy.

Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM.

Recently, one-transistor dynamic random-access memory (1T-DRAM) cells having a polysilicon body (poly-Si 1T-DRAM) have attracted attention as candidates to replace conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Poly-Si 1T-DRAM enables the cost-effective implementation of a silicon-on-insulator (SOI) structure and a three-dimensional (3D) stacked architecture for increasing integration density. However, studies on the transient characteristics of poly-Si 1T-DRAM are still lacking. In this paper, with TCAD simulation, we examine the differences between the memory mechanisms in poly-Si and silicon body 1T-DRAM. A silicon 1T-DRAM cell's data state is determined by the number of holes stored in a floating body (FB), while a poly-Si 1T-DRAM cell's state depends on the number of electrons trapped in its grain boundary (GB). This means that a poly-Si 1T-DRAM can perform memory operations by using GB as a storage region in thin body devices with a small FB area.

Memristor Neural Network Training with Clock Synchronous Neuromorphic System.

Memristor devices are considered to have the potential to implement unsupervised learning, especially spike timing-dependent plasticity (STDP), in the field of neuromorphic hardware research. In this study, a neuromorphic hardware system for multilayer unsupervised learning was designed, and unsupervised learning was performed with a memristor neural network. We showed that the nonlinear characteristic memristor neural network can be trained by unsupervised learning only with the correlation between inputs and outputs. Moreover, a method to train nonlinear memristor devices in a supervised manner, named guide training, was devised. Memristor devices have a nonlinear characteristic, which makes implementing machine learning algorithms, such as backpropagation, difficult. The guide-training algorithm devised in this paper updates the synaptic weights by only using the correlations between inputs and outputs, and therefore, neither complex mathematical formulas nor computations are required during the training. Thus, it is considered appropriate to train a nonlinear memristor neural network. All training and inference simulations were performed using the designed neuromorphic hardware system. With the system and memristor neural network, the image classification was successfully done using both the Hebbian unsupervised training and guide supervised training methods.

Analysis of the Memristor-Based Crossbar Synapse for Neuromorphic Systems.

In this study, we analyzed the memristor device typically used as a synapse in neuromorphic architecture and confirmed that the synaptic memristor device can be adopted to perform the machine learning algorithm. The nonlinear characteristics of the memristor complicates its use as the neuromorphic hardware in an artificial neural network (ANN) with a back-propagation algorithm. Using a memristor device with a nonlinear characteristic, we demonstrated that pattern classification can be implemented in ANNs using the Guide training algorithm without back-propagation. Furthermore, the memristor characteristics required to achieve accurate learning results are analyzed.