A Single-Chip 64-Channel Ultrasound RX-Beamformer Including Analog Front-End and an LUT for Non-Uniform ADC-Sample-Clock Generation.

A 64-channel RX digital beamformer was implemented in a single chip for 3-D ultrasound medical imaging using 2-D phased-array transducers. The RX beamformer chip includes 64 analog front-end branches including 64 non-uniform sampling ADCs, a FIFO/Adder, and an on-chip look-up table (LUT). The LUT stores the information on the rising edge timing of the non-uniform ADC sampling clocks. To include the LUT inside the beamformer chip, the LUT size was reduced by around 240 times by approximating an ADC-sample-time profile w.r.t. focal points (FP) along a scanline (SL) for a channel into a piece-wise linear form. The maximum error between the approximated and accurate sample times of ADC is eight times the sample time resolution (Ts) that is 1/32 of the ultrasound signal period in this work. The non-uniform sampling reduces the FIFO size required for digital beamforming by around 20 times. By applying a 9-dot image from Field-II program and 2-D ultrasound phantom images to the fabricated RX beamformer chip, the original images were successfully reconstructed from the measured output. The chip in a 0.13-um CMOS occupies 30.25 [Formula: see text] and consumes 605 mW.

An analog-digital hybrid RX beamformer chip with non-uniform sampling for ultrasound medical imaging with 2D CMUT array.

To reduce the memory area, a two-stage RX beamformer (BF) chip with 64 channels is proposed for the ultrasound medical imaging with a 2D CMUT array. The chip retrieved successfully two B-mode phantom images with a steering angle from -45 (°) to +45 (°), the maximum delay range of 8 µs, and the delay resolution of 6.25 ns. An analog-digital hybrid BF (HBF) is chosen for the proposed chip to utilize the easy beamforming operation in the digital domain and also to reduce chip area by minimizing the number of ADCs. The chip consists of eight analog beamformers (ABF) for the 1st-stage and a digital beamformer (DBF) for the 2nd-stage. The two-stage architecture reduces the memory area of both ABF and DBF by around four times. The DBF circuit is divided into three steps to further reduce the digital FIFO memory area by around twice. Coupled with the non-uniform sampling scheme, the proposed two-stage HBF chip reduces the total memory area by around 40 times compared to the uniform-sampling single-stage BF chip. The chip fabricated in a 0.13- µm CMOS process occupies the area of 19.4 mm(2), and dissipates 1.14 W with the analog supply of 3.3 V and the digital supply of 1.2 V.