Mechanical and Electrical Reliability Analysis of Flexible Si Complementary Metal-Oxide-Semiconductor Integrated Circuit.

A flexible Si complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) with multi-level interconnects is realized by thinning down and transferring the CMOS IC onto a polymer substrate. A detailed mechanical and electrical reliability analysis of the flexible Si CMOS IC is carried out in relation to the neutral mechanical plane (NMP) that is extracted from both analytical and numerical modeling. To enhance the reliability by optimizing the NMP position, the thicknesses of all the layers in the CMOS IC on the polymer substrate are carefully adjusted. The NMP-optimized flexible Si CMOS IC maintains its mechanical and electrical stability even at a 5-mm radius bending condition. In addition, to explore the degradation mechanism of the flexible Si CMOS IC, the change of the interface state density of the flexible Si CMOS at different bending conditions is investigated using the charge pumping method. Finally, the long-term electrical reliability of this flexible Si CMOS IC is also investigated.

Influence of Self-Heating Effect on Interface Trap Generation in Highly Flexible Single-Crystalline Si Nanomembrane Transistors.

We analyze the interface trap states generated by the self-heating effect in flexible single-crystalline Si nanomembrane (sc-Si NM) transistors. Despite the excellent device performance (Subthreshold swing: ~61 mV/dec, Ion/off: ~109, Nit: ~5 × 1010 cm-2, µeff: ~250 cm²/V·s) and mechanical flexibility (RB,min ═ 1 mm) of sc-Si NM transistors on a polymer substrate, they are vulnerable to thermal reliability issues due to the poor thermal conductivity (κ < 1 W/m·K) of the polymer substrate. Understanding the detailed mechanism driving heat-related device degradation is key to improving device reliability, life expectancy, and overall device performance. Thus, a charge pumping method was employed to systematically analyze the device degradation caused by the self-heating effect. This enabled the interface trap density to be investigated for the flexible sc-Si NM transistors on a polymer substrate after a bias stress. For comparison, a heat spreading layer (HSL) made using a 1-µm thick Ag film (κ~400 W/m·K) was integrated into the sc-Si NM device to mitigate the self-heating effect. The results showed that the interface trap density was proportional to the self-heating effect. This facilitated the fundamental understanding of the self-heating effect of flexible sc-Si NM transistors, opening a robust route to realizing high performance flexible devices using sc-Si NM.

A High-Performance Top-Gated Graphene Field-Effect Transistor with Excellent Flexibility Enabled by an iCVD Copolymer Gate Dielectric.

A high-performance top-gated graphene field-effect transistor (FET) with excellent mechanical flexibility is demonstrated by implementing a surface-energy-engineered copolymer gate dielectric via a solvent-free process called initiated chemical vapor deposition. The ultrathin, flexible copolymer dielectric is synthesized from two monomers composed of 1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane and 1-vinylimidazole (VIDZ). The copolymer dielectric enables the graphene device to exhibit excellent dielectric performance and substantially enhanced mechanical flexibility. The p-doping level of the graphene can be tuned by varying the polar VIDZ fraction in the copolymer dielectric, and the Dirac voltage (VDirac ) of the graphene FET can thus be systematically controlled. In particular, the VDirac approaches neutrality with higher VIDZ concentrations in the copolymer dielectric, which minimizes the carrier scattering and thereby improves the charge transport of the graphene device. As a result, the graphene FET with 20 nm thick copolymer dielectrics exhibits field-effect hole and electron mobility values of over 7200 and 3800 cm2 V-1 s-1 , respectively, at room temperature. These electrical characteristics remain unchanged even at the 1 mm bending radius, corresponding to a tensile strain of 1.28%. The formed gate stack with the copolymer gate dielectric is further investigated for high-frequency flexible device applications.

Vertically Formed Graphene Stripe for 3D Field-Effect Transistor Applications.

A 100-nm wide, vertically formed graphene stripe (GS) is demonstrated for three-dimensional (3D) electronic applications. The GS forms along the sidewall of a thin nickel film. It is possible to further scale down the GS width by engineering the deposited thickness of the atomic layer deposition (ALD) Ni film. Unlike a conventional GS or graphene nanoribbon (GNR), the vertically formed GS is made without a graphene transfer and etching process. The process integration of the proposed GS FETs resembles that of currently commercialized vertical NAND flash memory with a design rule of less than 20 nm, implying practical usage of this formed GS for 3D advanced FET applications.

Improved Drain Current Saturation and Voltage Gain in Graphene-on-Silicon Field Effect Transistors.

Graphene devices for radio frequency (RF) applications are of great interest due to their excellent carrier mobility and saturation velocity. However, the insufficient current saturation in graphene field effect transistors (FETs) is a barrier preventing enhancements of the maximum oscillation frequency and voltage gain, both of which should be improved for RF transistors. Achieving a high output resistance is therefore a crucial step for graphene to be utilized in RF applications. In the present study, we report high output resistances and voltage gains in graphene-on-silicon (GoS) FETs. This is achieved by utilizing bare silicon as a supporting substrate without an insulating layer under the graphene. The GoSFETs exhibit a maximum output resistance of 2.5 MΩ∙µm, maximum intrinsic voltage gain of 28 dB, and maximum voltage gain of 9 dB. This method opens a new route to overcome the limitations of conventional graphene-on-insulator (GoI) FETs and subsequently brings graphene electronics closer to practical usage.

Synthesis of ultrathin polymer insulating layers by initiated chemical vapour deposition for low-power soft electronics.

Insulating layers based on oxides and nitrides provide high capacitance, low leakage, high breakdown field and resistance to electrical stresses when used in electronic devices based on rigid substrates. However, their typically high process temperatures and brittleness make it difficult to achieve similar performance in flexible or organic electronics. Here, we show that poly(1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3) prepared via a one-step, solvent-free technique called initiated chemical vapour deposition (iCVD) is a versatile polymeric insulating layer that meets a wide range of requirements for next-generation electronic devices. Highly uniform and pure ultrathin films of pV3D3 with excellent insulating properties, a large energy gap (>8 eV), tunnelling-limited leakage characteristics and resistance to a tensile strain of up to 4% are demonstrated. The low process temperature, surface-growth character, and solvent-free nature of the iCVD process enable pV3D3 to be grown conformally on plastic substrates to yield flexible field-effect transistors as well as on a variety of channel layers, including organics, oxides, and graphene.

Facile graphene n-doping by wet chemical treatment for electronic applications.

We report a post-synthetic n-doping method for chemical-vapor-deposition (CVD) grown graphene using wet chemical processing. An ammonium fluoride solution was found effective in converting pristine hole doping into electron doping in addition to the mobility improvement of charge carriers. We verified the doping by electrical measurements, Raman spectroscopy and X-ray photoelectron spectroscopy (XPS) analyses and suggest that the mechanism of n-doping is electrostatic doping by ionic physisorption of ammonium ions on the graphene surface. This simple chemical doping method provides a facile and robust route to n-doping of large area graphene for the realization of high performance graphene-based electronic devices.

Functionalized graphene as an ultrathin seed layer for the atomic layer deposition of conformal high-k dielectrics on graphene.

Ultrathin functionalized graphene (FG) is demonstrated to work as an effective seed layer for the atomic layer deposition (ALD) of high-k dielectrics on graphene that is synthesized via chemical vapor deposition (CVD). The FG layer is prepared using a low-density oxygen plasma treatment on CVD graphene and is characterized using Raman spectroscopy and X-ray photoelectron spectroscopy (XPS). While the ALD deposition on graphene results in a patchy and rough dielectric deposition, the abundant oxygen species provided by the FG seed layer enable conformal and pinhole-free dielectric film deposition over the entire area of the graphene channel. The metal-insulator-graphene (MIG) capacitors fabricated with the FG-seeded Al2O3 exhibit superior scaling capabilities with low leakage currents when compared with the co-processed capacitors with Al seed layers.