Facet-selective group-III incorporation in InGaAs template assisted selective epitaxy.

InGaAs is a potential candidate for Si replacement in upcoming advanced technological nodes because of its excellent electron transport properties and relatively low interface defect density in dielectric gate stacks. Therefore, integrating InGaAs devices with the established Si platforms is highly important. Using template-assisted selective epitaxy (TASE), InGaAs nanowires can be monolithically integrated with high crystal quality, although the mechanisms of group III incorporation in this ternary material have not been thoroughly investigated. Here we present a detailed study of the compositional variations of InGaAs nanostructures epitaxially grown on Si(111) and Silicon-on-insulator substrates by TASE. We present a combination of XRD data and detailed EELS maps and find that the final Ga/In chemical composition depends strongly on both growth parameters and the growth facet type, leading to complex compositional sub-structures throughout the crystals. We can further conclude that the composition is governed by the facet-dependent chemical reaction rates at low temperature and low V/III ratio, while at higher temperature and V/III ratio, the incorporation is transport limited. In this case we see indications that the transport is a competition between Knudsen flow and surface diffusion.

Vertical III-V nanowire device integration on Si(100).

We report complementary metal-oxide-semiconductor (CMOS)-compatible integration of compound semiconductors on Si substrates. InAs and GaAs nanowires are selectively grown in vertical SiO2 nanotube templates fabricated on Si substrates of varying crystallographic orientations, including nanocrystalline Si. The nanowires investigated are epitaxially grown, single-crystalline, free from threading dislocations, and with an orientation and dimension directly given by the shape of the template. GaAs nanowires exhibit stable photoluminescence at room temperature, with a higher measured intensity when still surrounded by the template. Si-InAs heterojunction nanowire tunnel diodes were fabricated on Si(100) and are electrically characterized. The results indicate a high uniformity and scalability in the fabrication process.

Selective area growth of III-V nanowires and their heterostructures on silicon in a nanotube template: towards monolithic integration of nano-devices.

We demonstrate a catalyst-free growth technique to directly integrate III-V semiconducting nanowires on silicon using selective area epitaxy within a nanotube template. The nanotube template is selectively filled by homo- as well as heteroepitaxial growth of nanowires with the morphology entirely defined by the template geometry. To demonstrate the method single-crystalline InAs wires on Si as well as InAs-InSb axial heterostructure nanowires are grown within the template. The achieved heterointerface is very sharp and confined within 5-6 atomic planes which constitutes a primary advantage of this technique. Compared to metal-catalyzed or self-catalyzed nanowire growth processes, the nanotube template approach does not suffer from the often observed intermixing of (hetero-) interfaces and non-intentional core-shell formation. The sequential deposition of different material layers within a nanotube template can therefore serve as a general monolithic integration path for III-V based electronic and optoelectronic devices on silicon.

Carbon nanotube complementary wrap-gate transistors.

Among the challenges hindering the integration of carbon nanotube (CNT) transistors in digital technology are the lack of a scalable self-aligned gate and complementary n- and p-type devices. We report CNT transistors with self-aligned gates scaled down to 20 nm in the ideal gate-all-around geometry. Uniformity of the gate wrapping the nanotube channels is confirmed, and the process is shown not to damage the CNTs. Further, both n- and p-type transistors were realized by using the appropriate gate dielectric-HfO2 yielded n-type and Al2O3 yielded p-type-with quantum simulations used to explore the impact of important device parameters on performance. These discoveries not only provide a promising platform for further research into gate-all-around CNT devices but also demonstrate that scalable digital switches with realistic technological potential can be achieved with carbon nanotubes.

Sub-10 nm carbon nanotube transistor.

Although carbon nanotube (CNT) transistors have been promoted for years as a replacement for silicon technology, there is limited theoretical work and no experimental reports on how nanotubes will perform at sub-10 nm channel lengths. In this manuscript, we demonstrate the first sub-10 nm CNT transistor, which is shown to outperform the best competing silicon devices with more than four times the diameter-normalized current density (2.41 mA/µm) at a low operating voltage of 0.5 V. The nanotube transistor exhibits an impressively small inverse subthreshold slope of 94 mV/decade-nearly half of the value expected from a previous theoretical study. Numerical simulations show the critical role of the metal-CNT contacts in determining the performance of sub-10 nm channel length transistors, signifying the need for more accurate theoretical modeling of transport between the metal and nanotube. The superior low-voltage performance of the sub-10 nm CNT transistor proves the viability of nanotubes for consideration in future aggressively scaled transistor technologies.