High-κ Dielectric (HfO2)/2D Semiconductor (HfSe2) Gate Stack for Low-Power Steep-Switching Computing Devices.

Herein, a high-quality gate stack (native HfO2 formed on 2D HfSe2) fabricated via plasma oxidation is reported, realizing an atomically sharp interface with a suppressed interface trap density (Dit ≈ 5 × 1010 cm-2 eV-1). The chemically converted HfO2 exhibits dielectric constant, κ ≈ 23, resulting in low gate leakage current (≈10-3 A cm-2) at equivalent oxide thickness ≈0.5 nm. Density functional calculations indicate that the atomistic mechanism for achieving a high-quality interface is the possibility of O atoms replacing the Se atoms of the interfacial HfSe2 layer without a substitution energy barrier, allowing layer-by-layer oxidation to proceed. The field-effect-transistor-fabricated HfO2/HfSe2 gate stack demonstrates an almost ideal subthreshold slope (SS) of ≈61 mV dec-1 (over four orders of IDS) at room temperature (300 K), along with a high Ion/Ioff ratio of ≈108 and a small hysteresis of ≈10 mV. Furthermore, by utilizing a device architecture with separately controlled HfO2/HfSe2 gate stack and channel structures, an impact ionization field-effect transistor is fabricated that exhibits n-type steep-switching characteristics with a SS value of 3.43 mV dec-1 at room temperature, overcoming the Boltzmann limit. These results provide a significant step toward the realization of post-Si semiconducting devices for future energy-efficient data-centric computing electronics.

A steep-switching impact ionization-based threshold switching field-effect transistor.

A steep switching device with a low subthreshold swing (SS) that overcomes the fundamental Boltzmann limit (kT/q) is required to efficiently process a continuously increasing amount of data. Recently, two-dimensional material-based impact ionization transistors with various structures have been reported with the advantages of a low critical electric field and a unique quantum confinement effect. However, most of them cannot retain steep switching at room temperature, and device performance degradation issues caused by impact ionization-induced hot carriers have not been structurally addressed. In this study, we presented an impact-ionization-based threshold switching field-effect transistor (I2S-FET) fabricated with a serial connection of a MoS2 FET and WSe2 impact ionization-based threshold switch (I2S). We obtained repetitive operation with low SS (32.8 mV dec-1) at room temperature, along with low dielectric injection efficiency (10-6), through a structural design with separation of the conducting region, which determines on-state carrier transport, and the steep-switching region where the transition from off- to on-state occurs via impact ionization. Furthermore, compared to previously reported threshold-switching devices, our device demonstrated hysteresis-free switching characteristics. This study provides a promising approach for developing next-generation energy-efficient electronic devices and ultralow-power applications.

Anisotropy of impact ionization in WSe2 field effect transistors.

Carrier multiplication via impact ionization in two-dimensional (2D) layered materials is a very promising process for manufacturing high-performance devices because the multiplication has been reported to overcome thermodynamic conversion limits. Given that 2D layered materials exhibit highly anisotropic transport properties, understanding the directionally-dependent multiplication process is necessary for device applications. In this study, the anisotropy of carrier multiplication in the 2D layered material, WSe2, is investigated. To study the multiplication anisotropy of WSe2, both lateral and vertical WSe2 field effect transistors (FETs) are fabricated and their electrical and transport properties are investigated. We find that the multiplication anisotropy is much bigger than the transport anisotropy, i.e., the critical electric field (ECR) for impact ionization of vertical WSe2 FETs is approximately ten times higher than that of lateral FETs. To understand the experimental results we calculate the average energy of the carriers in the proposed devices under strong electric fields by using the Monte Carlo simulation method. The calculated average energy is strongly dependent on the transport directions and we find that the critical electric field for impact ionization in vertical devices is approximately one order of magnitude larger than that of the lateral devices, consistent with experimental results. Our findings provide new strategies for the future development of low-power electric and photoelectric devices.

A steep switching WSe2 impact ionization field-effect transistor.

The Fermi-Dirac distribution of carriers and the drift-diffusion mode of transport represent two fundamental barriers towards the reduction of the subthreshold slope (SS) and the optimization of the energy consumption of field-effect transistors. In this study, we report the realization of steep-slope impact ionization field-effect transistors (I2FETs) based on a gate-controlled homogeneous WSe2 lateral junction. The devices showed average SS down to 2.73 mV/dec over three decades of source-drain current and an on/off ratio of ~106 at room temperature and low bias voltages (<1 V). We determined that the lucky-drift mechanism of carriers is valid in WSe2, allowing our I2FETs to have high impact ionization coefficients and low SS at room temperature. Moreover, we fabricated a logic inverter based on a WSe2 I2FET and a MoS2 FET, exhibiting an inverter gain of 73 and almost ideal noise margin for high- and low-logic states. Our results provide a promising approach for developing functional devices as front runners for energy-efficient electronic device technology.

Complementary Driving between 2D Heterostructures and Surface Functionalization for Surpassing Binary Logic Devices.

Recently, for overcoming the fundamental limits of conventional silicon technology, multivalued logic (MVL) circuits based on two-dimensional (2D) materials have received significant attention for reducing the power consumption and the complexity of integrated circuits. Compared with the conventional silicon complementary metal oxide semiconductor technology, new functional heterostructures comprising 2D materials can be readily implemented, owing to their unique inherent electrical properties. Furthermore, their process integration does not pose issues of lattice mismatch at junction interfaces. This facilitates the realization of new functional logic gate circuit configurations. However, the reported three-valued NOT gates (ternary inverters) based on 2D materials require stringent operating conditions and complex fabrication processes to obtain three distinct logic states. Herein, a general structure of MVL devices based on a simple series connection of 2D materials with partial surface functionalization is demonstrated. By arranging three 2D materials exhibiting p-type, ambipolar, and n-type conductivities, ternary inverter circuits can be established based on the complementary driving between 2D heterotransistors. This ternary inverter circuit can be further improved for quaternary inverter circuits by controlling the charge neutral point of partial ambipolar 2D materials using surface functionalization, which is an effective and nondestructive doping method for 2D materials.

Homogeneous platinum diselenide metal/semiconductor coplanar structure fabricated by selective thickness control.

For the realization of two-dimensional material-based high-performance electronic devices, the formation of a stable, high-quality metal-semiconductor contact is a key factor. Platinum diselenide (PtSe2), a group-10 transition metal dichalcogenide, is a promising candidate owing to its unique property of layer-dependent semiconductor-to-semimetal transition. Here, a scalable and controllable method utilizing an inductively coupled plasma treatment is reported for selectively controlling the thickness of PtSe2 flakes. The PtSe2 transforms from a semimetal to a semiconductor when the thickness decreases below 3 nm. A field-effect transistor is fabricated based on the homogeneous platinum diselenide metal/semiconductor coplanar structure (metallic PtSe2 as source/drain electrodes and semiconductor PtSe2 as a channel), which demonstrates a low contact resistance of 362 Ωµm and carrier mobility of 150 cm2 V-1 s-1, outperforming the previously reported PtSe2-based devices.