Demonstration of a novel majority logic in a memristive crossbar array for in-memory parallel computing.

A memristive crossbar array can execute Boolean logic operations directly within the memory, which is highly noteworthy as it addresses the data bottleneck issue in traditional von Neumann computing. Although its potential has been widely demonstrated, achieving practical levels of operational reliability and computational efficiency remains a challenge. Here, we introduce a three-input majority logic gate supported by near-memory operations, serving as a universal gate and achieving both robust reliability and high efficiency in versatile logic operations. We fabricated a highly reliable HfOx-based memristive array, incorporating a series resistor to increase the reset voltage of the memristor, thereby increasing the operational voltage margin of the gate operation. This ensured reliable operation of the majority gate, resulting in successful experimental proof of combined 1-bit full adder and subtractor operations performed in 5 steps using 7 cells. Additionally, we propose that an N-bit parallel prefix adder (PPA) operation is possible in O(log2 N) steps, by taking advantage of the parallel operation capability of the majority gate. This achieves 8.5× higher spatiotemporal efficiency than the previously reported NOR-based logic system in 64-bit adder operation. Moreover, as N increases, the spatiotemporal efficiency further improves, which significantly enhances the applicability of memristive logic-in-memory.

Memristive Explainable Artificial Intelligence Hardware.

Artificial intelligence (AI) is often considered a black box because it provides optimal answers without clear insight into its decision-making process. To address this black box problem, explainable artificial intelligence (XAI) has emerged, which provides an explanation and interpretation of its decisions, thereby promoting the trustworthiness of AI systems. Here, a memristive XAI hardware framework is presented. This framework incorporates three distinct types of memristors (Mott memristor, valence change memristor, and charge trap memristor), each responsible for performing three essential functions (perturbation, analog multiplication, and integration) required for the XAI hardware implementation. Three memristor arrays with high robustness are fabricated and the image recognition of 3 × 3 testing patterns and their explanation map generation are experimentally demonstrated. Then, a software-based extended system based on the characteristics of this hardware is built, simulating a large-scale image recognition task. The proposed system can perform the XAI operations with only 4.32% of the energy compared to conventional digital systems, enlightening its strong potential for the XAI accelerator.