The Intersection of Machine Learning and Wireless Sensor Network Security for Cyber-Attack Detection: A Detailed Analysis.

This study provides a thorough examination of the important intersection of Wireless Sensor Networks (WSNs) with machine learning (ML) for improving security. WSNs play critical roles in a wide range of applications, but their inherent constraints create unique security challenges. To address these problems, numerous ML algorithms have been used to improve WSN security, with a special emphasis on their advantages and disadvantages. Notable difficulties include localisation, coverage, anomaly detection, congestion control, and Quality of Service (QoS), emphasising the need for innovation. This study provides insights into the beneficial potential of ML in bolstering WSN security through a comprehensive review of existing experiments. This study emphasises the need to use ML's potential while expertly resolving subtle nuances to preserve the integrity and dependability of WSNs in the increasingly interconnected environment.

an-QNA: An Adaptive Nesterov Quasi-Newton Acceleration-Optimized CMOS LNA for 65 nm Automotive Radar Applications.

An adaptive Nesterov quasi-Newton acceleration (an-QNA)-optimized low-noise amplifier (LNA) is proposed in this paper. An optimized single-ended-to-differential two-stage LNA circuit is presented. It includes an improved post-linearization (IPL) technique to enhance the linearity. Traditional methods like conventional quasi-Newton (c-QN) often suffer from slow convergence and the tendency to get trapped in local minima. However, the proposed an-QNA method significantly accelerates the convergence speed. Furthermore, in this paper, modifications have been made to the an-QNA algorithm using a quadratic estimation to guarantee global convergence. The optimized an-QNA-based LNA, using standard 65 nm CMOS technology, achieves a simulated gain of 17.5 dB, a noise figure (NF) of 3.7 dB, and a 1 dB input compression point (IP1dB) of -13.1 dBm. It is also noted that the optimized LNA achieves a measured gain of 12.9 dB and an NF of 4.98 dB, and the IP1dB is -17.8 dB. The optimized LNA has a chip area of 0.67 mm2.

Dual Features, Compact Dimensions and X-Band Applications for the Design and Fabrication of Annular Circular Ring-Based Crescent-Moon-Shaped Microstrip Patch Antenna.

This study uses annular circular rings to create multi-band applications using crescent-shaped patch antennas. It is designed to be made up of five circular, annular rings nested inside of each other. Three annular rings are positioned and merged on top of the larger rings, with two annular rings set along the bottom of the feed line. The factors that set them apart, such as bandwidths, radiation patterns, gain, impedance, and return loss (RL), are analysed. The outcomes show how compact the multi-band annular ring antenna is. The proposed circular annular ring antenna has return losses of -33 dB and operates at two frequencies: 3.1 GHz and 9.3 GHz. This design is modelled and simulated using ANSYS HFSS. The outcomes of the simulation and the tests agree quite well. The X band and WLAN resonant bands have bandwidth capacities of 500 and 4300 MHz, respectively. Additionally, the circular annular ring antenna design is advantageous for most services at these operating bands.

A Reformed PSO-Based High Linear Optimized Up-Conversion Mixer for Radar Application.

A reformed particle swarm optimization (RPSO)-based up-conversion mixer circuit is proposed for radar application in this paper. In practice, a non-optimized up-conversion mixer suffers from high power consumption, poor linearity, and conversion gain. Therefore, the RPSO algorithm is proposed to optimize the up-conversion mixer. The novelty of the proposed RPSO algorithm is it helps to solve the problem of local optima and premature convergence in traditional particle swarm optimization (TPSO). Furthermore, in the RPSO, a velocity position-based convergence (VPC) and wavelet mutation (WM) strategy are used to enhance RPSO's swarm diversity. Moreover, this work also features novel circuit configurations based on the two-fold transconductance path (TTP), a technique used to improve linearity. A differential common source (DCS) amplifier is included in the primary transconductance path (PTP) of the TTP. As for the subsidiary transconductance path (STP), the enhanced cross-quad transconductor (ECQT) is implemented within the TTP. A benchmark function verification is conducted to demonstrate the effectiveness of the RPSO algorithm. The proposed RPSO has also been compared with other optimization algorithms such as the genetic algorithm (GA) and the non-dominated sorting genetic algorithm II (NSGA-II). By using RPSO, the proposed optimized mixer achieves a conversion gain (CG) of 2.5 dB (measured). In this study, the proposed mixer achieves a 1 dB compression point (OP1dB) of 4.2 dBm with a high linearity. In the proposed mixer, the noise figure (NF) is approximately 3.1 dB. While the power dissipation of the optimized mixer is 3.24 mW. Additionally, the average time for RPSO to design an up-conversion mixer is 4.535 s. Simulation and measured results demonstrate the excellent performance of the RPSO optimized up-conversion mixer.

Front-End Development for Radar Applications: A Focus on 24 GHz Transmitter Design.

The proliferation of radar technology has given rise to a growing demand for advanced, high-performance transmitter front-ends operating in the 24 GHz frequency band. This paper presents a design analysis of a radio frequency (RF) transmitter (TX) front-end operated at a 24 GHz frequency and designed using 65 nm complementary metal-oxide-semiconductor (CMOS) technology for radar applications. The proposed TX front-end design includes the integration of an up-conversion mixer and power amplifier (PA). The up-conversion mixer is a Gilbert cell-based design that translates the 2.4 GHz intermediate frequency (IF) signal and 21.6 GHz local oscillator (LO) signal to the 24 GHz RF output signal. The mixer is designed with a novel technique that includes a duplex transconductance path (DTP) for enhancing the mixer's linearity. The DTP of the mixer includes a primary transconductance path (PTP) and a secondary transconductance path (STP). The PTP incorporates a common source (CS) amplifier, while the STP incorporates an improved cross-quad transconductor (ICQT). The integrated PA in the TX front-end is a class AB tunable two-stage PA that can be tuned with the help of varactors as a synchronous mode to increase the PA bandwidth or stagger mode to obtain a high gain. The PA is tuned to 24 GHz as a synchronous mode PA for the TX front-end operation. The proposed TX front-end showed an excellent output power of 11.7 dBm and dissipated 7.5 mW from a 1.2 V supply. In addition, the TX front-end achieved a power-added efficiency (PAE) of 47% and 1 dB compression point (OP1dB) of 10.5 dBm. In this case, the output power is 10.5 dBm higher than the linear portion of the response. The methodologies presented herein have the potential to advance the state of the art in 24 GHz radar technology, fostering innovations in fields such as autonomous vehicles, industrial automation, and remote sensing.

Pattern Classification Using Quantized Neural Networks for FPGA-Based Low-Power IoT Devices.

With the recent growth of the Internet of Things (IoT) and the demand for faster computation, quantized neural networks (QNNs) or QNN-enabled IoT can offer better performance than conventional convolution neural networks (CNNs). With the aim of reducing memory access costs and increasing the computation efficiency, QNN-enabled devices are expected to transform numerous industrial applications with lower processing latency and power consumption. Another form of QNN is the binarized neural network (BNN), which has 2 bits of quantized levels. In this paper, CNN-, QNN-, and BNN-based pattern recognition techniques are implemented and analyzed on an FPGA. The FPGA hardware acts as an IoT device due to connectivity with the cloud, and QNN and BNN are considered to offer better performance in terms of low power and low resource use on hardware platforms. The CNN and QNN implementation and their comparative analysis are analyzed based on their accuracy, weight bit error, RoC curve, and execution speed. The paper also discusses various approaches that can be deployed for optimizing various CNN and QNN models with additionally available tools. The work is performed on the Xilinx Zynq 7020 series Pynq Z2 board, which serves as our FPGA-based low-power IoT device. The MNIST and CIFAR-10 databases are considered for simulation and experimentation. The work shows that the accuracy is 95.5% and 79.22% for the MNIST and CIFAR-10 databases, respectively, for full precision (32-bit), and the execution time is 5.8 ms and 18 ms for the MNIST and CIFAR-10 databases, respectively, for full precision (32-bit).

A Novel 65 nm Active-Inductor-Based VCO with Improved Q-Factor for 24 GHz Automotive Radar Applications.

The inductor was primarily developed on a low-voltage CMOS tunable active inductor (CTAI) for radar applications. Technically, the factors to be considered for VCO design are power consumption, low silicon area, high frequency with reasonable phase noise, an immense quality (Q) factor, and a large frequency tuning range (FTR). We used CMOS tunable active inductor (TAI) topology relying on cascode methodology for 24 GHz frequency operation. The newly configured TAI adopts the additive capacitor (Cad) with the cascode approach, and in the subthreshold region, one of the transistors functions as the TAI. The study, simulations, and measurements were performed using 65nm CMOS technology. The assembled circuit yields a spectrum from 21.79 to 29.92 GHz output frequency that enables sustainable platforms for K-band and Ka-band operations. The proposed design of TAI demonstrates a maximum Q-factor of 6825, and desirable phase noise variations of -112.43 and -133.27 dBc/Hz at 1 and 10 MHz offset frequencies for the VCO, respectively. Further, it includes enhanced power consumption that varies from 12.61 to 23.12 mW and a noise figure (NF) of 3.28 dB for a 24 GHz radar application under a low supply voltage of 0.9 V.

A 65 nm Duplex Transconductance Path Up-Conversion Mixer for 24 GHz Automotive Short-Range Radar Sensor Applications.

A 24 GHz highly-linear upconversion mixer, based on a duplex transconductance path (DTP), is proposed for automotive short-range radar sensor applications using the 65-nm CMOS process. A mixer with an enhanced transconductance stage consisting of a DTP is presented to improve linearity. The main transconductance path (MTP) of the DTP includes a common source (CS) amplifier, while the secondary transconductance path (STP) of the DTP is implemented as an improved cross-quad transconductor (ICQT). Two inductors with a bypass capacitor are connected at the common nodes of the transconductance stage and switching stage of the mixer, which acts as a resonator and helps to improve the gain and isolation of the designed mixer. According to the measured results, at 24 GHz the proposed mixer shows that the linearity of output 1-dB compression point (OP1dB) is 3.9 dBm. And the input 1-dB compression point (IP1dB) is 0.9 dBm. Moreover, a maximum conversion gain (CG) of 2.49 dB and a noise figure (NF) of 3.9 dB is achieved in the designed mixer. When the supply voltage is 1.2 V, the power dissipation of the mixer is 3.24 mW. The mixer chip occupies an area of 0.42 mm2.

A Novel Optimized V-VLC Receiver Sensor Design Using µGA in Automotive Applications.

Vehicular visible light communication is known as a promising way of inter-vehicle communication. Vehicular VLC can ensure the significant advancement of safety and efficiency in traffic. It has disadvantages, such as unexpected glare on drivers in moving conditions, i.e., non-line-of-sight link at night. While designing a receiver, the most important factor is to ensure the optimal quality of the received signal. Within this context, to achieve an optimal communication quality, it is necessary to find the optimal maximum signal strength. Hereafter, a new receiver design is focused on in this paper at the circuit level, and a novel micro genetic algorithm is proposed to optimize the signal strength. The receiver can calculate the SNR, and it is possible to modify its structural design. The micro GA determines the alignment of the maximum signal strength at the receiver point rather than monitoring the signal strength for each angle. The results showed that the proposed scheme accurately estimates the alignment of the receiver, which gives the optimum signal strength. In comparison with the conventional GA, the micro GA results showed that the maximum received signal strength was improved by -1.7 dBm, -2.6 dBm for user Location 1 and user Location 2, respectively, which proves that the micro GA is more efficient. The execution time of the conventional GA was 7.1 s, while the micro GA showed 0.7 s. Furthermore, at a low SNR, the receiver showed robust communication for automotive applications.

Design and Analysis of a Novel 24 GHz Up-Conversion Mixer with Improved Derivative Super-Position Linearizer Technique for 5G Applications.

A 24 GHz high linear, high-gain up-conversion mixer is realized for fifth-generation (5G) applications in the 65 nm CMOS process. The mixer's linearity is increased by applying an Improved Derivative Super-Position (I-DS) technique cascaded between the mixer's transconductance and switching stage. The high gain and stability of amplifiers in the transconductance stage of the mixer are achieved using novel tunable capacitive cross-coupled common source (TCC-CS) transistors. Using the I-DS, the third-order non-linear coefficient of current is closed to zero, enhancing the linearity. Additionally, a TCC-CS, which is realized by varactors, neutralizes the gate-to-drain parasitic capacitance (Cgd) of transistors in the transconductance stage of the mixer and contributes to the improvement of the gain and stability of the mixer. The measured 1 dB compression point OP1dB of the designed mixer is 4.1 dBm and IP1dB is 0.67 dBm at 24 GHz. The conversion gain of 4.1 dB at 24 GHz and 3.2 ± 0.9 dB, from 20 to 30 GHz is achieved in the designed mixer. Furthermore, a noise figure of 3.8 dB is noted at 24 GHz. The power consumption of the mixer is 4.9 mW at 1.2 V, while the chip area of the designed mixer is 0.4 mm2.