RESUMO
The complexity of systems with parallel acquisition architectures has increased sharply with the continuous growth of signal bandwidth, and sampling precision has been greatly challenged. Considering that the signal to be measured usually exhibits sparsity in the frequency domain, this paper proposes a re-configurable bandwidth interleaved acquisition architecture to maximize test flexibility and accuracy. The sampling process is divided into two stages: sensing and re-configurable acquisition. In the sensing stage, the signal spectrum distribution is roughly understood using a sparse Fourier transform. Based on the spectrum sensing results, the subband selection and the adaptive adjustment of the mixing local oscillator in the acquisition system are performed. Ultimately, these steps enhance sampling accuracy. This paper verifies the effectiveness of this method on a 10 GHz acquisition system, demonstrating that it can significantly reduce data redundancy. In addition, it improves acquisition accuracy compared to traditional bandwidth interleaved systems. The experimental results indicate that re-configurable sampling can significantly improve the quality of sampling results. This is evidenced by a signal-to-noise ratio improvement of over 7.4 dB and a spurious-free dynamic range improvement of over 4.7 dB compared to traditional sampling results.
RESUMO
To satisfy the input bandwidth and sampling rate requirements of data acquisition systems, digital bandwidth-interleaved analog-to-digital converters (DBI-ADCs) offer a practical parallel structure. However, the existing DBI-ADC correction methods are broadly inadequate in terms of design, testing, and implementation. Moreover, the evaluation and correction of the most significant feature of the DBI-ADC structure-wideband acquisition performance-is also imperfect. This paper proposes an itemized correction method for DBI-ADC structures. The proposed method simplifies the complex correction filter bank design algorithm into multiple simple correction filters and then separates and corrects the various errors of the DBI-ADC system. This dramatically simplifies the design, testing, and implementation process of the system, resulting in a highly convenient method for practical engineering. In addition, this method achieves a good correction effect, with an appropriate balance between the correction effect and the project implementation. Simulation results and experimental results verify the effectiveness of the proposed method.
RESUMO
The time-interleaved (TI) structure has been widely implemented in high speed, wideband data acquisition systems to increase the system sampling rate. However, the frequency responses of each sub-sampling path are not identical. This is named frequency response mismatches (FRMs). In TI-based printed circuit board level systems, due to the impact of the parasitic parameters, the FRMs are more complicated than the mismatches in TI analog-to-digital converters (TIADCs), which degrade the system performance severely. Therefore, the FRM calibration in 2-channel TI acquisition systems with two features is researched. The first one is that the TI system has a larger mismatch range than in most previous research. The second one is that the channel frequency response uses the general model. The calibration structure is established by the analysis of the digital TI model, which implements the TI operation in the digital domain to reconstruct the mismatches in the time domain. Furthermore, the problem of designing an arbitrary frequency response filter is transformed to the question of designing a three-stage cascaded filter group, which gives a method to realize the arbitrary frequency response in a real system. An oscilloscope prototype is proposed to verify the calibration performance. The simulation and experiment show the following: (i) Even though it uses the general frequency response and the FRMs are significant, the proposed method is still effective. (ii) The mismatch range of magnitude and phase responses is highly suppressed, and the spurious-free dynamic range is improved by 16.26 dB after calibration of the prototype.
RESUMO
Memory depth represents an oscilloscope's capability to continuously acquire and store sampling points at the highest real-time sampling rate. Improving the memory depth is conducive to improving the system's capability to analyze waveform details, but it will slow down the response time of the system. This paper proposes a high-speed deep memory data acquisition system with a real-time sampling rate of up to 10 GSPS and a memory depth up to 1 Gpts based on ultra-high-speed parallel sampling, waveform quick positioning and zooming, and waveform 3D mapping and display. This study focuses on the use of waveform quick positioning and zooming techniques under deep memory conditions to solve the slow response time and low waveform capture rate that are the result of improving the memory depth. This paper gives the experimental results for real-time signal data acquisition. The results show that adopting waveform quick positioning and zooming techniques achieved the following aims: significantly improved system response time, rapid positioning and display waveform details available to users, fast waveform capture rate and improved oscilloscope performance.
RESUMO
The acquisition of waveforms and the analysis of transient characteristics of signals are the fundamental tasks for time-domain measurement, while the reduction of the measuring gap till seamless measurement is extremely important to the acquisition, measurement, and analysis of transient signals. This paper, aimed at the seamless time-domain measurement of non-stationary transient signals, proposes an approximate entropy-based characteristic signal extraction algorithm on the basis of information entropy theories. The algorithm quantitatively describes the complexity (amount of information) of sampled signals using the approximate entropy value, self-adaptively captures characteristic signals under the control of the approximate entropy in real time, extracts the critical or useful information, and removes redundant or useless information so as to reduce the time consumption of processing data and displaying waveforms and realize the seamless time-domain measurement of transient signals finally. Experimental results show that the study could provide a new method for the design of electronic measuring instrument with seamless measurement capability.
RESUMO
Parallelism-based technique of time-interleaved analog-to-digital conversion (TIADC) has become an effective solution for the higher sampling rate acquisition system to acquire non-repetitive waveforms. With the increase of sampling frequency, the indeterminacy of combining sequence of sampled data among multiple components has become a highlighted barrier for the reset operation of high-speed acquisition systems, and this is especially obvious for the ultra-fast TIADC systems. In this paper, we clarify the root of the problem in multiple-component synchronization (MCS) caused by such reset operation. Also we propose a novel and reliable hardware solution to precisely condition each reset signal, including three key circuit design parameters, i.e., the best time interval, required edge uncertainty, and the minimum delay precision. Besides, the designing scheme and debugging procedures are presented in detail in a generalized platform of this system type. Finally, in order to demonstrate the feasibility, parametric materialization and testing verification are gradually accomplished in a 20 Giga Samples Per Second (GSPS) TIADC system composed of four 5 GSPS ADC components. The results show that the proposed method is feasible and effective for ensuring the combined determinacy of multiple groups of sampled data and solving the MCS problem. In comparison with other existing solutions, it adopts some simple logic components more easily and flexibly, and this is significant for the development of congeneric systems or instruments featuring the MCS.