Mobility and current boosting of In-Ga-Zn-O thin-film transistors with metal capping layer oxidation.

This study investigates the effect of an oxidized Ta capping layer on the boosting of field-effect mobility (µFE) of amorphous In-Ga-Zn-O (a-IGZO) Thin-film transistors (TFTs). The oxidation of Ta creates additional oxygen vacancies on the a-IGZO channel surface, leading to increased carrier density. We investigate the effect of increasing Ta coverage on threshold voltage (Vth), on-state current,µFEand gate bias stress stability of a-IGZO TFTs. A significant increase inµFEof over 8 fold, from 16 cm2Vs-1to 140 cm2Vs-1, was demonstrated with the Ta capping layer covering 90% of the channel surface. By partial leaving the a-IGZO uncovered at the contact region, a potential barrier region was created, maintaining the low off-state current and keeping the threshold voltage near 0 V, while the capped region operated as a carrier-boosted region, enhancing channel conduction. The results reported in this study present a novel methodology for realizing high-performance oxide semiconductor devices. The demonstrated approach holds promise for a wide range of next-generation device applications, offering new avenues for advancement in metal oxide semiconductor TFTs.

Improved high voltage operation of amorphous In-Ga-Zn-O thin film transistor by carrier density enhancement.

We report on improved high voltage operation of amorphous-In-Ga-Zn-O (a-IGZO) thin film transistors (TFTs) by increasing carrier density and distributing the high bias field over the length of the device which utilizes an off-set drain structure. By decreasing the O2partial pressure during sputter deposition of IGZO, the channel carrier density of the high voltage a-IGZO TFT (HiVIT) was increased to ∼1018cm-3. Which reduced channel resistance and therefore the voltage drop in the ungated offset region during the on-state. To further decrease the electric field in the offset region, we applied Ta capping and subsequent oxidation to locally increase the oxygen vacancy levels in the offset region thereby increasing local carrier density. The reduction of the drain field in the offset region from 1.90 Vµm-1to 1.46 Vµm-1at 200 V drain voltage, significantly improved the operational stability of the device by reducing high field degradation. At an extreme drain voltage of 500 V, the device showed an off-state current of ∼10-11A and on-state current of ∼1.59 mA demonstrating that with further enhancements the HiVIT may be applicable to thin-film form, low leakage, high voltage control applications.

An Ultralow Power Mixed Dimensional Heterojunction Transistor Based on the Charge Plasma pn Junction.

Development of a reliable doping method for 2D materials is a key issue to adopt the materials in the future microelectronic circuits and to replace the silicon, keeping the Moore's law toward the sub-10 nm channel length. Especially hole doping is highly required, because most of the transition metal dichalcogenides (TMDC) among the 2D materials are electron-doped by sulfur vacancies in their atomic structures. Here, hole doping of a TMDC, tungsten disulfide (WS2 ) using the silicon substrate as the dopant medium is demonstrated. An ultralow-power current sourcing transistor or a gated WS2 pn diode is fabricated based on a charge plasma pn heterojunction formed between the WS2 thin-film and heavily doped bulk silicon. An ultralow switchable output current down to 0.01 nA µm-1 , an off-state current of ≈1 × 10-14 A µm-1 , a static power consumption range of 1 fW µm-1 -1 pW µm-1 , and an output current ratio of 103 at 0.1 V supply voltage are achieved. The charge plasma heterojunction allows a stable (less than 3% variation) output current regardless of the gate voltage once it is turned on.

Layered deposition of SnS2 grown by atomic layer deposition and its transport properties.

In this work, we report on the layered deposition of few-layer tin disulfide (SnS2) using atomic layer deposition (ALD). By varying the ALD cycles it was possible to deposit poly-crystalline SnS2 with small variation in layer numbers. Based on the ALD technique, we developed the process technology growing few-layer crystalline SnS2 film (3-6 layers) and we investigated their electrical properties by fabricating bottom-gated thin film transistors using the ALD SnS2 as the transport channel. SnS2 devices showed typical n-type characteristic with on/off current ratio of ∼8.32 × 106, threshold voltage of ∼2 V, and a subthreshold swing value of 830 mV decade-1 for the 6 layers SnS2. The developed SnS2 ALD technique may aid the realization of two-dimensional SnS2 based flexible and wearable devices.