Oxide and 2D TMD semiconductors for 3D DRAM cell transistors.

As the downscaling of conventional dynamic random-access memory (DRAM) has reached its limits, 3D DRAM has been proposed as a next-generation DRAM cell architecture. However, incorporating silicon into 3D DRAM technology faces various challenges in securing cost-effective high cell transistor performance. Therefore, many researchers are exploring the application of next-generation semiconductor materials, such as transition oxide semiconductors (OSs) and metal dichalcogenides (TMDs), to address these challenges and to realize 3D DRAM. This study provides an overview of the proposed structures for 3D DRAM, compares the characteristics of OSs and TMDs, and discusses the feasibility of employing the OSs and TMDs as the channel material for 3D DRAM. Furthermore, we review recent progress in 3D DRAM using the OSs, discussing their potential to overcome challenges in silicon-based approaches.

High-κ Dielectric (HfO2)/2D Semiconductor (HfSe2) Gate Stack for Low-Power Steep-Switching Computing Devices.

Herein, a high-quality gate stack (native HfO2 formed on 2D HfSe2) fabricated via plasma oxidation is reported, realizing an atomically sharp interface with a suppressed interface trap density (Dit ≈ 5 × 1010 cm-2 eV-1). The chemically converted HfO2 exhibits dielectric constant, κ ≈ 23, resulting in low gate leakage current (≈10-3 A cm-2) at equivalent oxide thickness ≈0.5 nm. Density functional calculations indicate that the atomistic mechanism for achieving a high-quality interface is the possibility of O atoms replacing the Se atoms of the interfacial HfSe2 layer without a substitution energy barrier, allowing layer-by-layer oxidation to proceed. The field-effect-transistor-fabricated HfO2/HfSe2 gate stack demonstrates an almost ideal subthreshold slope (SS) of ≈61 mV dec-1 (over four orders of IDS) at room temperature (300 K), along with a high Ion/Ioff ratio of ≈108 and a small hysteresis of ≈10 mV. Furthermore, by utilizing a device architecture with separately controlled HfO2/HfSe2 gate stack and channel structures, an impact ionization field-effect transistor is fabricated that exhibits n-type steep-switching characteristics with a SS value of 3.43 mV dec-1 at room temperature, overcoming the Boltzmann limit. These results provide a significant step toward the realization of post-Si semiconducting devices for future energy-efficient data-centric computing electronics.

Well-Balanced Ambipolar Charge Transport of Diketopyrrolepyrrole-Based Copolymers: Organic Field-Effect Transistors and High-Voltage Logic Applications.

A poly (3,6-bis(thiophen-2-yl)-2,5-bis(2-decyltetradecyl)-2,5-dihydropyrrolo[3,4-c]pyrrole-1,4-dione-co-(2,3-bis(phenyl)acrylonitrile)) (PDPADPP) copolymer, composed of diketopyrrolopyrrole (DPP) and a cyano (nitrile) group with a vinylene spacer linking two benzene rings, is synthesized via a palladium-catalyzed Suzuki coupling reaction. The electrical performance of PDPADPP in organic field-effect transistors (OFETs) and circuits is investigated. The OFETs based on PDPADPP exhibit typical ambipolar transport characteristics, with the as-cast OFETs demonstrating low field-effect hole and electron mobility values of 0.016 and 0.004 cm2  V-1  s-1 , respectively. However, after thermal annealing at 240 °C, the OFETs exhibit improved transport characteristics with highly balanced ambipolar transport, showing average hole and electron mobility values of 0.065 and 0.116 cm2  V-1  s-1 , respectively. To verify the application of the PDPADPP OFETs in high-voltage logic circuits, compact modeling using the industry-standard small-signal Berkeley short-channel IGFET model (BSIM) is performed, and the logic application characteristics are evaluated. The circuit simulation results demonstrate excellent logic application performance of the PDPADPP-based ambipolar transistor and illustrate that the device annealed at 240 °C exhibits ideal circuit characteristics.

Modulation of Contact Resistance of Dual-Gated MoS2 FETs Using Fermi-Level Pinning-Free Antimony Semi-Metal Contacts.

Achieving low contact resistance (RC ) is one of the major challenges in producing 2D FETs for future CMOS technology applications. In this work, the electrical characteristics for semimetal (Sb) and normal metal (Ti) contacted MoS2 devices are systematically analyzed as a function of top and bottom gate-voltages (VTG and VBG ). The semimetal contacts not only significantly reduce RC but also induce a strong dependence of RC on VTG , in sharp contrast to Ti contacts that only modulate RC by varying VBG . The anomalous behavior is attributed to the strongly modulated pseudo-junction resistance (Rjun ) by VTG , resulting from weak Fermi level pinning (FLP) of Sb contacts. In contrast, the resistances under both metallic contacts remain unchanged by VTG as metal screens the electric field from the applied VTG . Technology computer aided design simulations further confirm the contribution of VTG to Rjun , which improves overall RC of Sb-contacted MoS2 devices. Consequently, the Sb contact has a distinctive merit in dual-gated (DG) device structure, as it greatly reduces RC and enables effective gate control by both VBG and VTG . The results offer new insight into the development of DG 2D FETs with enhanced contact properties realized by using semimetals.

Hyper-FET's Phase-Transition-Materials Design Guidelines for Ultra-Low Power Applications at 3 nm Technology Node.

In this work, a hybrid-phase transition field-effects-transistor (hyper-FET) integrated with phase-transition materials (PTM) and a multi-nanosheet FET (mNS-FET) at the 3 nm technology node were analyzed at the device and circuit level. Through this, a benchmark was performed for presenting device design guidelines and for using ultra-low-power applications. We present an optimization flow considering hyper-FET characteristics at the device and circuit level, and analyze hyper-FET performance according to the phase transition time (TT) and baseline-FET off-leakage current (IOFF) variations of the PTM. As a result of inverter ring oscillator (INV RO) circuit analysis, the optimized hyper-FET increases speed by +8.74% and reduces power consumption by -16.55%, with IOFF = 5 nA of baseline-FET and PTM TT = 50 ps compared to the conventional mNS-FET in the ultra-low-power region. As a result of SRAM circuit analysis, the read static noise margin is improved by 43.9%, and static power is reduced by 58.6% in the near-threshold voltage region when the PTM is connected to the pull-down transistor source terminal of 6T SRAM for high density. This is achieved at 41% read current penalty.