RESUMO
As a promising alternative to the von Neumann architecture, in-memory computing holds the promise of delivering a high computing capacity while consuming low power. In this paper, we show that the ferroelectric reconfigurable transistor can serve as a versatile logic-in-memory unit that can perform logic operations and data storage concurrently. When functioning as memory, a ferroelectric reconfigurable transistor can implement content-addressable memory (CAM) with a 1-transistor-per-bit density. With the switchable polarity of the ferroelectric reconfigurable transistor, XOR/XNOR-like matching operation in CAM is realized in a single transistor, which can offer a significant improvement in area and energy efficiency compared to conventional CAMs. NAND- and NOR-arrays of CAMs are also demonstrated, which enable multibit matching in a single reading operation. In addition, the NOR array of CAM cells effectively measures the Hamming distance between the input query and the stored entries. When functioning as a logic element, a ferroelectric reconfigurable transistor can be switched between n- and p-type modes. Utilizing the switchable polarity of these ferroelectric Schottky barrier transistors, we demonstrate reconfigurable logic gates with NAND/NOR dual functions, whose input-output mapping can be transformed in real time without changing the layout, and the configuration is nonvolatile.
RESUMO
In this paper, we demonstrate low-thermal-budget ferroelectric field-effect transistors (FeFETs) based on the two-dimensional ferroelectric CuInP2S6 (CIPS) and oxide semiconductor InZnO (IZO). The CIPS/IZO FeFETs exhibit nonvolatile memory windows of â¼1 V, low off-state drain currents, and high carrier mobilities. The ferroelectric CIPS layer serves a dual purpose by providing electrostatic doping in IZO and acting as a passivation layer for the IZO channel. We also investigate the CIPS/IZO FeFETs as artificial synaptic devices for neural networks. The CIPS/IZO synapse demonstrates a sizable dynamic ratio (125) and maintains stable multilevel states. Neural networks based on CIPS/IZO FeFETs achieve an accuracy rate of over 80% in recognizing MNIST handwritten digits. These ferroelectric transistors can be vertically stacked on silicon complementary metal-oxide semiconductor (CMOS) with a low thermal budget, offering broad applications in CMOS+X technologies and energy-efficient 3D neural networks.
RESUMO
Lateral multiheterostructures with spatially modulated bandgaps have great potential for applications in high-performance electronic, optoelectronic and thermoelectric devices. Multiheterostructures based on transition metal tellurides are especially promising due to their tunable bandgap in a wide range and the rich variety of structural phases. However, the synthesis of telluride-based multiheterostructures remains a challenge due to the low activity of tellurium and the poor thermal stability of tellurium alloys. In this work, we synthesized monolayer WSe2-2xTe2x/WSe2-2yTe2y (x > y) multiheterostructures in situ using chemical vapor deposition (CVD). Photoluminescence analysis and Raman mapping confirm the spatial modulation of the bandgap in the radial direction. Furthermore, field-effect transistors with the channels parallel (type I) and perpendicular (type II) to the multiheterostructure rings were fabricated. Type I transistors exhibit enhanced ambipolar transport, due to the low energy bridges between the source and drain. Remarkably, the photocurrents in type I transistors are two orders of magnitude higher than those in type II transistors, which can be attributed to the fact that the photovoltaic photocurrents generated at the two heterojunctions are summed together in type I transistors, but they cancel each other in type II transistors. These multiheterostructures will provide a new platform for novel electronic/photonic devices with potential applications in broadband light sensing, highly sensitive imaging and ultrafast optoelectronic integrated circuits.
RESUMO
Maintaining fast charging capability at low temperatures represents a significant challenge for supercapacitors. The performance of conventional porous carbon electrodes often deteriorates quickly with the decrease of temperature due to sluggish ion and charge transport. Here we fabricate a 3D-printed multiscale porous carbon aerogel (3D-MCA) via a unique combination of chemical methods and the direct ink writing technique. 3D-MCA has an open porous structure with a large surface area of â¼1750 m2 g-1. At -70 °C, the symmetric device achieves outstanding capacitance of 148.6 F g-1 at 5 mV s-1. Significantly, it retains a capacitance of 71.4 F g-1 at a high scan rate of 200 mV s-1, which is 6.5 times higher than the non-3D printed MCA. These values rank among the best results reported for low temperature supercapacitors. These impressive results highlight the essential role of open porous structures for preserving capacitive performance at ultralow temperatures.
RESUMO
Device engineering based on the tunable electronic properties of ternary transition metal dichalcogenides has recently gained widespread research interest. In this work, monolayer ternary telluride core/shell structures are synthesized using a one-step chemical vapor deposition process with rapid cooling. The core region is the tellurium-rich WSe2-2 x Te2 x alloy, while the shell is the tellurium-poor WSe2-2 y Te2 y alloy. The bandgap of the material is ≈1.45 eV in the core region and ≈1.57 eV in the shell region. The lateral gradient of the bandgap across the monolayer heterostructure allows for the fabrication of heterogeneous transistors and photodetectors. The difference in work function between the core and shell regions leads to a built-in electric field at the heterojunction. As a result, heterogeneous transistors demonstrate a unidirectional conduction and strong photovoltaic effect. The bandgap gradient and high mobility of the ternary telluride core/shell structures provide a unique material platform for novel electronic and photonic devices.
RESUMO
The performance of pseudocapacitive electrodes at fast charging rates are typically limited by the slow kinetics of Faradaic reactions and sluggish ion diffusion in the bulk structure. This is particularly problematic for thick electrodes and electrodes highly loaded with active materials. Here, a surface-functionalized 3D-printed graphene aerogel (SF-3D GA) is presented that achieves not only a benchmark areal capacitance of 2195 mF cm-2 at a high current density of 100 mA cm-2 but also an ultrahigh intrinsic capacitance of 309.1 µF cm-2 even at a high mass loading of 12.8 mg cm-2 . Importantly, the kinetic analysis reveals that the capacitance of SF-3D GA electrode is primarily (93.3%) contributed from fast kinetic processes. This is because the 3D-printed electrode has an open structure that ensures excellent coverage of functional groups on carbon surface and facilitates the ion accessibility of these surface functional groups even at high current densities and large mass loading/electrode thickness. An asymmetric device assembled with SF-3D GA as anode and 3D-printed GA decorated with MnO2 as cathode achieves a remarkable energy density of 0.65 mWh cm-2 at an ultrahigh power density of 164.5 mW cm-2 , outperforming carbon-based supercapacitors operated at the same power density.