Power measurement methods for energy efficient applications.

Energy consumption constraints on computing systems are more important than ever. Maintenance costs for high performance systems are limiting the applicability of processing devices with large dissipation power. New solutions are needed to increase both the computation capability and the power efficiency. Moreover, energy efficient applications should balance performance vs. consumption. Therefore power data of components are important. This work presents the most remarkable alternatives to measure the power consumption of different types of computing systems, describing the advantages and limitations of available power measurement systems. Finally, a methodology is proposed to select the right power consumption measurement system taking into account precision of the measure, scalability and controllability of the acquisition system.

Computational burden resulting from image recognition of high resolution radar sensors.

This paper presents a methodology for high resolution radar image generation and automatic target recognition emphasizing the computational cost involved in the process. In order to obtain focused inverse synthetic aperture radar (ISAR) images certain signal processing algorithms must be applied to the information sensed by the radar. From actual data collected by radar the stages and algorithms needed to obtain ISAR images are revised, including high resolution range profile generation, motion compensation and ISAR formation. Target recognition is achieved by comparing the generated set of actual ISAR images with a database of ISAR images generated by electromagnetic software. High resolution radar image generation and target recognition processes are burdensome and time consuming, so to determine the most suitable implementation platform the analysis of the computational complexity is of great interest. To this end and since target identification must be completed in real time, computational burden of both processes the generation and comparison with a database is explained separately. Conclusions are drawn about implementation platforms and calculation efficiency in order to reduce time consumption in a possible future implementation.

Parametric dense stereovision implementation on a system-on chip (SoC).

This paper proposes a novel hardware implementation of a dense recovery of stereovision 3D measurements. Traditionally 3D stereo systems have imposed the maximum number of stereo correspondences, introducing a large restriction on artificial vision algorithms. The proposed system-on-chip (SoC) provides great performance and efficiency, with a scalable architecture available for many different situations, addressing real time processing of stereo image flow. Using double buffering techniques properly combined with pipelined processing, the use of reconfigurable hardware achieves a parametrisable SoC which gives the designer the opportunity to decide its right dimension and features. The proposed architecture does not need any external memory because the processing is done as image flow arrives. Our SoC provides 3D data directly without the storage of whole stereo images. Our goal is to obtain high processing speed while maintaining the accuracy of 3D data using minimum resources. Configurable parameters may be controlled by later/parallel stages of the vision algorithm executed on an embedded processor. Considering hardware FPGA clock of 100 MHz, image flows up to 50 frames per second (fps) of dense stereo maps of more than 30,000 depth points could be obtained considering 2 Mpix images, with a minimum initial latency. The implementation of computer vision algorithms on reconfigurable hardware, explicitly low level processing, opens up the prospect of its use in autonomous systems, and they can act as a coprocessor to reconstruct 3D images with high density information in real time.

Efficient smart CMOS camera based on FPGAs oriented to embedded image processing.

This article describes an image processing system based on an intelligent ad-hoc camera, whose two principle elements are a high speed 1.2 megapixel Complementary Metal Oxide Semiconductor (CMOS) sensor and a Field Programmable Gate Array (FPGA). The latter is used to control the various sensor parameter configurations and, where desired, to receive and process the images captured by the CMOS sensor. The flexibility and versatility offered by the new FPGA families makes it possible to incorporate microprocessors into these reconfigurable devices, and these are normally used for highly sequential tasks unsuitable for parallelization in hardware. For the present study, we used a Xilinx XC4VFX12 FPGA, which contains an internal Power PC (PPC) microprocessor. In turn, this contains a standalone system which manages the FPGA image processing hardware and endows the system with multiple software options for processing the images captured by the CMOS sensor. The system also incorporates an Ethernet channel for sending processed and unprocessed images from the FPGA to a remote node. Consequently, it is possible to visualize and configure system operation and captured and/or processed images remotely.

A focusing method in the calibration process of image sensors based on IOFBs.

A focusing procedure in the calibration process of image sensors based on Incoherent Optical Fiber Bundles (IOFBs) is described using the information extracted from fibers. These procedures differ from any other currently known focusing method due to the non spatial in-out correspondence between fibers, which produces a natural codification of the image to transmit. Focus measuring is essential prior to carrying out calibration in order to guarantee accurate processing and decoding. Four algorithms have been developed to estimate the focus measure; two methods based on mean grey level, and the other two based on variance. In this paper, a few simple focus measures are defined and compared. Some experimental results referred to the focus measure and the accuracy of the developed methods are discussed in order to demonstrate its effectiveness.

An intelligent architecture based on Field Programmable Gate Arrays designed to detect moving objects by using Principal Component Analysis.

This paper presents a complete implementation of the Principal Component Analysis (PCA) algorithm in Field Programmable Gate Array (FPGA) devices applied to high rate background segmentation of images. The classical sequential execution of different parts of the PCA algorithm has been parallelized. This parallelization has led to the specific development and implementation in hardware of the different stages of PCA, such as computation of the correlation matrix, matrix diagonalization using the Jacobi method and subspace projections of images. On the application side, the paper presents a motion detection algorithm, also entirely implemented on the FPGA, and based on the developed PCA core. This consists of dynamically thresholding the differences between the input image and the one obtained by expressing the input image using the PCA linear subspace previously obtained as a background model. The proposal achieves a high ratio of processed images (up to 120 frames per second) and high quality segmentation results, with a completely embedded and reliable hardware architecture based on commercial CMOS sensors and FPGA devices.

Sensor for high speed, high precision measurement of 2-d positions.

A sensor system to measure the 2-D position of an object that intercepts a plane in space is presented in this paper. This sensor system was developed with the aim of measuring the height and lateral position of contact wires supplying power to electric locomotives. The sensor comprises two line-scans focused on the zone to be measured and positioned in such a way that their viewing planes are on the same plane. The report includes a mathematical model of the sensor system, and details the method used for calibrating the sensor system. The procedure used for high speed measurement of object position in space is also described, where measurement acquisition time was less than 0.7 ms. Finally, position measurement results verifying system performance in real time are given.

Sensor for distance measurement using pixel grey-level information.

An alternative method for distance measurement is presented, based on a radiometric approach to the image formation process. The proposed methodology uses images from an infrared emitting diode (IRED) to estimate the distance between the camera and the IRED. Camera output grey-level intensities are a function of the accumulated image irradiance, which is also related by inverse distance square law to the distance between the camera and the IRED. Analyzing camera-IRED distance, magnitudes that affected image grey-level intensities, and therefore accumulated image irradiance, were integrated into a differential model which was calibrated and used for distance estimation over a 200 to 600 cm range. In a preliminary model, the camera and the emitter were aligned.

Sensor for Distance Estimation Using FFT of Images.

In this paper, the problem of how to estimate the distance between an infrared emitter diode (IRED) and a camera from pixel grey-level intensities is examined from a practical standpoint. Magnitudes that affect grey level intensity were defined and related to the zero frequency component from the FFT image. A general model was also described and tested for distance estimation over the range from 420 to 800 cm using a differential methodology. Method accuracy is over 3%.

Sensor Calibration Based on Incoherent Optical Fiber Bundles (IOFB) Used For Remote Image Transmission.

Image transmission using incoherent optical fiber bundles (IOFB) requires prior calibration to obtain the spatial in-out fiber correspondence in order to reconstruct the image captured by the pseudo-sensor. This information is recorded in a Look-Up Table (LUT), used later for reordering the fiber positions and reconstructing the original image. This paper presents a method based on line-scan to obtain the in-out correspondence. The results demonstrate that this technique yields a remarkable reduction in processing time and increased image quality by introducing a fiber detection algorithm, an intensity compensation process and finally, a single interpolation algorithm.

Predictive factors for early mortality following liver transplantation.

AIMS: To retrospectively review our liver transplant performance to identify factors that influenced early outcomes and to prospectively test their validity in predicting outcomes. METHODS: Clinical records from 190 patients with liver transplants (LT; n = 200) performed between 1991 and 1997 were reviewed and the data evaluated by univariate and multivariate analyses regarding clinical outcome. The prognostic model thus obtained was prospectively evaluated in 55 patients undergoing transplant between 1999 and 2000. RESULTS: Main indication for transplant was post-necrotic cirrhosis (61%), mostly HCV(+). The majority of patients were Child-Pugh C status (46%). Post-operative mortality at 3 months was 15.3%. Risk factors predicting death were: Child-Pugh C status (OR 1.3), pre-LT renal insufficiency (OR 5.8), malnutrition (OR 2.9) and technically complex surgery requiring cross-clamping with or without bypass (OR 4.9). None of the donor factors was significant. Prospectively applied to predict outcome in the 55 patients, the model had a sensitivity of 80% and a specificity of 88.8% with a higher-than-anticipated accuracy with a positive predictive value of 61.5% and a negative predictive value of 95.3%. CONCLUSIONS: Pre-LT renal insufficiency is the most significant risk factor for early mortality and suggests that LT should be performed before evidence of irreversible renal insufficiency becomes manifest.