A text analytics approach for mining public discussions in online cancer forum: Analysis of multi-intent lung cancer treatment dataset.

BACKGROUND: Online cancer forums (OCF) are increasingly popular platforms for patients and caregivers to discuss, seek information on, and share opinions about diseases and treatments. This interaction generates a substantial amount of unstructured text data, necessitating deeper exploration. Using time series data, our study exploits topic modeling in the novel domain of online cancer forums (OCFs) to identify meaningful topics and changing dynamics of online discussion across different lung cancer treatment intent groups. METHODS: For this purpose, a dataset comprising 27,998 forum posts about lung cancer was collected from three OCFs: lungcancer.net, lungevity.org, and reddit.com, spanning the years 2016 to 2018. RESULTS: The analysis reflects the public discussion on multi-intent lung cancer treatment over time, taking into account seasonal variations. Discussions on cancer symptoms and prevention garnered the most attention, dominating both curative and palliative care discussions. There were distinct seasonal peaks: curative care topics surged from winter to late spring, while palliative care topics peaked from late summer to mid-autumn. Keyword analysis highlighted that lung cancer diagnosis and treatment were primary topics, whereas cancer prevention and treatment outcomes were predominant across multi-care contexts. For the study period, curative care discussions predominantly revolved around informational support and disease syndromes. In contrast, social support and cancer prevention prevailed in the palliative care context. Notably, topics such as cancer screening and cancer treatment exhibit pronounced seasonal variations in curative care, peaking in frequency during the summers (May to August) of the study period. Meanwhile, the topic of tumor control within palliative care showed significant seasonal influence during the winters and summers of 2017 and 2018. CONCLUSION: Our text analysis approach using OCF data shows potential for computational methods in this novel domain to gain insights into trends in public cancer communication and seasonal variations for a better understanding of improving personalized care, decision support, treatment outcomes, and quality of life.

Design of a Current Sensing System with TIA Gain of 160 dBΩ and Input-Referred Noise of 1.8 pArms for Biosensor.

This paper proposes a high-gain low-noise current signal detection system for biosensors. When the biomaterial is attached to the biosensor, the current flowing through the bias voltage is changed so that the biomaterial can be sensed. A resistive feedback transimpedance amplifier (TIA) is used for the biosensor requiring a bias voltage. Current changes in the biosensor can be checked by plotting the current value of the biosensor in real time on the self-made graphical user interface (GUI). Even if the bias voltage changes, the input voltage of the analog to digital converter (ADC) does not change, so it is designed to plot the current of the biosensor accurately and stably. In particular, for multi-biosensors with an array structure, a method of automatically calibrating the current between biosensors by controlling the gate bias voltage of the biosensors is proposed. Input-referred noise is reduced using a high-gain TIA and chopper technique. The proposed circuit achieves 1.8 pArms input-referred noise with a gain of 160 dBΩ and is implemented in a TSMC 130 nm CMOS process. The chip area is 2.3 mm2, and the power consumption of the current sensing system is 12 mW.

A Design of Analog Front-End with DBPSK Demodulator for Magnetic Field Wireless Network Sensors.

This paper presents an on-chip fully integrated analog front-end (AFE) with a non-coherent digital binary phase-shift keying (DBPSK) demodulator suitable for short-range magnetic field wireless communication applications. The proposed non-coherent DBPSK demodulator is designed based on using comparators to digitize the received differential analog BPSK signal. The DBPSK demodulator does not need any phase-lock loop (PLL) to detect the data and recover the clock. Moreover, the proposed demodulator provides the detected data and the recovered clock simultaneously. Even though previous studies have offered the basic structure of the AFEs, this work tries to amplify and generate the required differential BPSK signal without missing data and clock throughout the AFE, while a low voltage level signal is received at the input of the AFE. A DC-offset cancellation (DCOC), a cascaded variable gain amplifier (VGA), and a single-to-differential (STOD) converter are employed to construct the implemented AFE. The simulation results indicate that the AFE provides a dynamic range of 0 dB to 40 dB power gain with 2 dB resolution. Measurement results show the minimum detectable voltage at the input of AFE is obtained at 20 mV peak-to-peak. The AFE and the proposed DBSPK demodulator are analyzed and fabricated in a 130 nm Bipolar-CMOS-DMOS (BCD) technology to recover the maximum data rate of 32 kbps where the carrier frequency is 128 kHz. The implemented DCOC, cascaded VGA, STOD, and the demodulator occupy 0.15 mm2, 0.063 mm2, 0.045 mm2, and 0.03 mm2 of area, respectively. The AFE and the demodulator consume 2.9 mA and 0.15 mA of current from an external 5 V power supply, respectively.

A Design of 10-Bit Asynchronous SAR ADC with an On-Chip Bandgap Reference Voltage Generator.

A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology. To optimize the power consumption, static, and dynamic performance, several techniques have been proposed. A dual-path bootstrap switch was proposed to increase the linearity sampling. The Voltage Common Mode (VCM)-based Capacitive Digital-to-Analog Converter (CDAC) switching technique was implemented for the CDAC part to alleviate the switching energy problem of the capacitive DAC. The proposed architecture of the two-stage dynamic latch comparator provides high speed and low power consumption. Moreover, to achieve faster bit conversion with an efficient time sequence, asynchronous SAR logic with an internally generated clock is implemented, which avoids the requirement of a high-frequency external clock, as all conversions are carried out in a single clock cycle. The proposed error amplifier-based bandgap reference voltage generator provides a stable reference voltage to the ADC for practical implementation. The measurement results of the proposed SAR ADC, including an on-chip bandgap reference voltage generator, show an Effective Number of Bits (ENOB) of 9.49 bits and Signal-to-Noise and Distortion Ratio (SNDR) of 58.88 dB with 1.2 V of power supply while operating with a sampling rate of 1 MS/s.

A High-Power 3P3T Cross Antenna Switch with Low Harmonic Distortion and Enhanced Isolation Using T-Type Pull-Down Path for Cellular Mobile Devices.

This paper presents a radio frequency (RF) triple pole triple throw 3P3T cross antenna switch for cellular mobile devices. The negative biasing scheme was applied to improve the power-handling capability and linearity of the switch by increasing the maximum tolerable voltage drop across the drain and source and reverse biasing the parasitic junction diodes. To avoid signal reflection through the antenna in off-state, all the antenna ports were equipped with 50-ohm termination to provide the pull-down path. Considering the simultaneous operation of antenna ports in different switch cases, the presented T-type pull-down path demonstrated improvement of isolation by over 15 dB. Using stacked switches, the 3P3T handled the input power level of over 35 dBm. The chip was manufactured in 65 nm complementary metal oxide semiconductor (CMOS) silicon on insulator (SOI) technology with a die size of 790 × 730 µm. The proposed structure achieved insertion loss, isolation, and voltage standing wave ratio (VSWR) of less than -0.9 dB, -40 dB, and 1.6, respectively, when the input signal was 3.8 GHz. The measured results prove the implemented switch shows the second and third harmonic distortion performances of less than -60 dBm when the input power level and frequency are 25 dBm and 3.8 GHz, respectively.

A 1.8-2.7 GHz Triple-Band Low Noise Amplifier with 31.5 dB Dynamic Range of Power Gain and Adaptive Power Consumption for LTE Application.

This paper presents a multi-gain radio frequency (RF) front-end low noise amplifier (LNA) utilizing a multi-core based on the source degeneration topology. The LNA can cover a wide range of input and output frequency matching by using a receiver (RX) switch at the input and a capacitor bank at the output of the LNA. In the proposed architecture here, to avoid the saturation of RX chain, 12 gain steps including positive, 0 dB, and negative power gains are controlled by a mobile industry processor interface (MIPI). The multi-core architecture offers the ability to control the power consumption over different gain steps. In order to avoid the phase discontinuity, the negative gain steps are provided using an active amplification and T-type attenuation path that keeps the phase discontinuity below ±5 degrees between two adjacent power gain steps. Using the multi-core structure, the power consumption is optimized in different power gains. The structure is enhanced with the adaptive variable cores and reactance parameters to maintain different power consumption for different gain steps and remain the output matching in an acceptable operating range. Furthermore, auxiliary linearization circuitries are added to improve the input third intercept point (IIP3) performance of the LNA. The chip is fabricated in 65 nm complementary metal-oxide semiconductor (CMOS) silicon on insulator (SOI) process and the die area is 0.308 mm2. The proposed architecture achieves the IIP3 performance of -10.2 dBm and 8.6 dBm in the highest and lowest power gains, which are 20.5 dB and -11 dB, respectively. It offers the noise figure (NF) performance of 1.15 dB in the highest power gain while it reaches 14 dB when the power gain is -11 dB. The LNA consumes 16.8 mA and 1.33 mA current from a 1 V power supply that is provided by an on-chip low-dropout (LDO) when it operates at the highest and lowest gains, respectively.

A Low-Power Analog Processor-in-Memory-Based Convolutional Neural Network for Biosensor Applications.

This paper presents an on-chip implementation of an analog processor-in-memory (PIM)-based convolutional neural network (CNN) in a biosensor. The operator was designed with low power to implement CNN as an on-chip device on the biosensor, which consists of plates of 32 × 32 material. In this paper, 10T SRAM-based analog PIM, which performs multiple and average (MAV) operations with multiplication and accumulation (MAC), is used as a filter to implement CNN at low power. PIM proceeds with MAV operations, with feature extraction as a filter, using an analog method. To prepare the input feature, an input matrix is formed by scanning a 32 × 32 biosensor based on a digital controller operating at 32 MHz frequency. Memory reuse techniques were applied to the analog SRAM filter, which is the core of low power implementation, and in order to accurately grasp the MAC operational efficiency and classification, we modeled and trained numerous input features based on biosignal data, confirming the classification. When the learned weight data was input, 19 mW of power was consumed during analog-based MAC operation. The implementation showed an energy efficiency of 5.38 TOPS/W and was differentiated through the implementation of 8 bits of high resolution in the 180 nm CMOS process.

A Dual-Band 47-dB Dynamic Range 0.5-dB/Step DPA with Dual-Path Power-Combining Structure for NB-IoT.

This paper presents a digital power amplifier (DPA) with a 43-dB dynamic range and 0.5-dB/step gain steps for a narrow-band Internet of Things (NBIoT) transceiver application. The proposed DPA is implemented in a dual-band architecture for both the low band and high band of the frequency coverage in an NBIoT application. The proposed DPA is implemented in two individual paths, power amplification, and power attenuation, to provide a wide range when both paths are implemented. To perform the fine control over the gain steps, ten fully differential cascode power amplifier cores, in parallel with a binary sizing, are used to amplify power and enable signals and provide fine gain steps. For the attenuation path, ten steps of attenuated signal level are provided which are controlled with ten power cores, similar to the power amplification path in parallel but with a fixed, small size for the cores. The proposed implementation is finalized with output custom-made baluns at the output. The technique of using parallel controlled cores provides a fine power adjustability by using a small area on the die where the NBIoT is fabricated in a 65-nm CMOS technology. Experimental results show a dynamic range of 47 dB with 0.5-dB fine steps are also available.

A Configurable and Fully Synthesizable RTL-Based Convolutional Neural Network for Biosensor Applications.

This paper presents a register-transistor level (RTL) based convolutional neural network (CNN) for biosensor applications. Biosensor-based diseases detection by DNA identification using biosensors is currently needed. We proposed a synthesizable RTL-based CNN architecture for this purpose. The adopted technique of parallel computation of multiplication and accumulation (MAC) approach optimizes the hardware overhead by significantly reducing the arithmetic calculation and achieves instant results. While multiplier bank sharing throughout the convolutional operation with fully connected operation significantly reduces the implementation area. The CNN model is trained in MATLAB® on MNIST® handwritten dataset. For validation, the image pixel array from MNIST® handwritten dataset is applied on proposed RTL-based CNN architecture for biosensor applications in ModelSim®. The consistency is checked with multiple test samples and 92% accuracy is achieved. The proposed idea is implemented in 28 nm CMOS technology. It occupies 9.986 mm2 of the total area. The power requirement is 2.93 W from 1.8 V supply. The total time taken is 8.6538 ms.

A Highly Efficient RF-DC Converter for Energy Harvesting Applications Using a Threshold Voltage Cancellation Scheme.

In this paper, a self-threshold voltage (Vth) compensated Radio Frequency to Direct Current (RF-DC) converter operating at 900 MHz and 2.4 GHz is proposed for RF energy harvesting applications. The threshold voltage of the rectifying devices is compensated by the bias voltage generated by the auxiliary transistors and output DC voltage. The auxiliary transistors compensate the threshold voltage (Vth) of the PMOS rectifying device while the threshold voltage (Vth) of the NMOS rectifying device is compensated by the output DC voltage. The proposed RF-DC converter was implemented in 180 nm Complementary Metal-Oxide Semiconductor (CMOS) technology. The experimental results show that the proposed design achieves better performance at both 900 MHz and 2.4 GHz frequencies in terms of PCE, output voltage, sensitivity, and effective area. The peak power conversion efficiency (PCE) of 38.5% at -12 dBm across a 1 MΩ load for 900 MHz frequency was achieved. Similarly, for 2.4 GHz frequency, the proposed circuit achieves a peak PCE of 26.5% at -6 dBm across a 1 MΩ load. The proposed RF-DC converter circuit shows a sensitivity of -20 dBm across a 1 MΩ load and produces a 1 V output DC voltage.

A 0.617-2.7 GHz Highly Linear High-Power Dual Port 15 Throws Antenna Switch Module (DP15T-ASM) with Branched-Antenna Technique and Termination Mode.

This paper presents a Dual-Port-15-Throw (DP15T) antenna switch module (ASM) Radio Frequency (RF) switch implemented by a branched antenna technique which has a high linearity for wireless communications and various frequency bands, including a low- frequency band of 617-960 MHz, a mid-frequency band of 1.4-2.2 GHz, and a high-frequency band of 2.3-2.7 GHz. To obtain an acceptable Insertion Loss (IL) and provide a consistent input for each throw, a branched antenna technique is proposed that distributes a unified magnetic field at the inputs of the throws. The other role of the proposed antenna is to increase the inductance effects for the closer ports to the antenna pad in order to decrease IL at higher frequencies. The module is enhanced by two termination modes for each antenna path to terminate the antenna when the switch is not operating. The module is fabricated in the silicon-on-insulator CMOS process. The measurement results show a maximum IMD2 and IMD3 of -100 dBm, while for the second and third harmonics the maximum value is -89 dBc. The module operates with a maximum power handling of 35 dBm. Experimental results show a maximum IL of 0.34 and 0.92 dB and a minimum isolation of 49 dB and 35.5 dB at 0.617 GHz and 2.7 GHz frequencies, respectively. The module is implemented in a compact way to occupy an area of 0.74 mm2. The termination modes show a second harmonic of 75 dBc, which is desirable.

T/R RF Switch with 150 ns Switching Time and over 100 dBc IMD for Wideband Mobile Applications in Thick Oxide SOI Process.

This paper presents a fast-switching Transmit/Receive (T/R) Single-Pole-Double-Throw (SPDT) Radio Frequency (RF) switch. Thorough analyses have been conducted to choose the optimum number of stacks, transistor sizes, gate and body voltages, to satisfy the required specifications. This switch applies six stacks of series and shunt transistors as big as 3.9 mm/160 nm and 0.75 mm/160 nm, respectively. A negative charge pump and a voltage booster generate the negative and boosted control voltages to improve the harmonics and to keep Inter-Modulation Distortion (IMD) performance of the switch over 100 dBc. A Low Drop-Out (LDO) regulator limits the boosted voltage in Absolute Maximum Rating (AMR) conditions and improves the switch performance for Process, Voltage and Temperature (PVT) variations. To reduce the size, a dense custom-made capacitor consisting of different types of capacitors has been presented where they have been placed over each other in layout considering the Design Rule Checks (DRC) and applied in negative charge pump, voltage booster and LDO. This switch has been fabricated and tested in a 90 nm Silicon-on-Insulator (SOI) process. The second and third IMD for all specified blockers remain over 100 dBc and the switching time as fast as 150 ns has been achieved. The Insertion Loss (IL) and isolation at 2.7 GHz are -0.17 dB and -33 dB, respectively. This design consumes 145 uA from supply voltage range of 1.65 V to 1.95 V and occupies 440 × 472 µm2 of die area.

The Role of Decreased Cortical Thickness and Volume of Medial Temporal Lobe Structures in Predicting Incident Psychosis in Patients With Alzheimer's Disease: A Prospective Longitudinal MRI Study.

OBJECTIVE: To investigate the effect of decreased cortical thickness or volume of medial temporal lobe structures on the risk of incident psychosis in patients with AD. DESIGN, SETTING, AND PARTICIPANTS: This hospital-based prospective longitudinal study enrolled 109 patients with AD. All patients with AD were evaluated at 3-month intervals to investigate the effect of decreased cortical thickness or volume of medial temporal lobe structures on the risk of incident psychosis in patients with AD. OUTCOME MEASURE: The main outcome measure was time-to-progression from AD to incident psychosis. The thickness or volume of medial temporal lobe structures (i.e., the hippocampus, entorhinal cortex, and parahippocampus) were measured using magnetic resonance imaging and the Freesurfer automated segmentation pipeline at baseline. RESULTS: Multivariate Cox proportional hazards regression analysis revealed that a decreased cortical thickness or volume of medial temporal region was associated with a higher risk of incident psychosis in patients with AD. The hazard ratios for decreased cortical thickness of the left entorhinal cortex and decreased cortical volume of the right hippocampus were 4.291 (95% confidence interval [CI], 1.196-15.384) and 2.680 [(CI, 1.003-1.196]), respectively. CONCLUSION: Our study revealed that decreased cortical thickness or volume of medial temporal sub-regions is a risk factor for incident psychosis in patients with AD. A careful assessment of the thickness or volume of the medial temporal lobe structures in AD may improve early detection and intervention of psychosis in AD.

A Low-Band Multi-Gain LNA Design for Diversity Receive Module with 1.2 dB NF.

This paper presents and discusses a Low-Band (LB) Low Noise Amplifier (LNA) design for a diversity receive module where the application is for multi-mode cellular handsets. The LB LNA covers the frequency range between 617 MHz to 960 MHz in 5 different frequency bands and a 5 Pole Single Throw (5PST) switch selects the different frequency bands where two of them are for the main and three for the auxiliary bands. The presented structure covers the gain modes from -12 to 18 dB with 6 dB gain steps where each gain mode has a different current consumption. In order to achieve the Noise Figure (NF) specifications in high gain modes, we have adopted a cascode Common-Source (CS) with inductive source degeneration structure for this design. To achieve the S11 parameters and current consumption specifications, the core and cascode transistors for high gain modes (18 dB, 12 dB, and 6 dB) and low gain modes (0 dB, -6 dB, and -12 dB) have been separated. Nevertheless, to keep the area low and keep the phase discontinuity within ±10∘, we have shared the degeneration and load inductors between two cores. To compensate the performance for Process, Voltage, and Temperature (PVT) variations, the structure applies a Low Drop-Out (LDO) regulator and a corner case voltage compensator. The design has been proceeded in a 65-nm RSB process design kit and the supply voltage is 1 V. For 18 dB and -12 dB gain modes as two examples, the NF, current consumption, and Input Third Order Intercept Point (IIP3) values are 1.2 dB and 16 dB, 10.8 mA and 1.2 mA, and -6 dBm and 8 dBm, respectively.

Mechanically Stable Kirigami Deformable Resonant Circuits for Wireless Vibration and Pressure Sensor Applications.

Deformable 3D structures have emerged to revolutionize next-generation flexible electronics. In this study, a large out-of-plane deformable kirigami-based structure integrated with traditional functional materials has been successfully applied to wirelessly sense mechanical vibration and pressure. Unlike spiral inductor coils that lack mechanical stability, the inductor coils supported with polymer kirigami designs, comprising concentric circles with alternately connected hinges among the consecutive layers, offer exceptional mechanical stability. The wireless sensor shows a good linear response (Adj. R2 = 0.99) between the shift in resonant frequency as a function of extension. Moreover, the sensor device exhibits excellent cycling mechanical stability and minimal hysteresis, as confirmed by the experiments performed for over 5 d. An acceleration sensor (0-20 ms-2) with high linearity (Adj. R2 = 0.99) is introduced. Furthermore, a highly sensitive low-pressure sensor is demonstrated wirelessly in real time. Thus, the sensor can wirelessly monitor mechanical vibration and pressure. It can be applied for motion tracking, health monitoring, soft robotics, and deformation detection in battery-free deformable electronic devices.

A 77-dB Dynamic-Range Analog Front-End for Fine-Dust Detection Systems with Dual-Mode Ultra-Low Noise TIA.

This paper presents an analog front-end for fine-dust detection systems with a 77-dB-wide dynamic range and a dual-mode ultra-low noise TIA with 142-dBΩ towards the maximum gain. The required high sensitivity of the analog signal conditioning path dictates having a high sensitivity at the front-end while the Input-Referred Noise (IRN) is kept low. Therefore, a TIA with a high sensitivity to detected current bio-signals is provided by a photodiode module. The analog front end is formed by the TIA, a DC-Offset Cancellation (DCOC) circuit, a Single-to-Differential Amplifier (SDA), and two Programmable Gain Amplifiers (PGAs). Gain adjustment is implemented by a coarse-gain-step using selective loads with four different gain values and fine-gain steps by 42 dB dynamic range during 16 fine steps. The settling time of the TIA is compensated using a capacitive compensation which is applied for the last stage. An off-state circuitry is proposed to avoid any off-current leakage. This TIA is designed in a 0.18 µm standard CMOS technology. Post-layout simulations show a high gain operation with a 67 dB dynamic range, input-referred noise, less than 600 fA/√Hz in low frequencies, and less than 27 fA/√Hz at 20 kHz, a minimum detectable current signal of 4 pA, and a 2.71 mW power consumption. After measuring the full path of the analog signal conditioning path, the experimental results of the fabricated chip show a maximum gain of 142 dB for the TIA. The Single-to-Differential Amplifier delivers a differential waveform with a unity gain. The PGA1 and PGA2 show a maximum gain of 6.7 dB and 6.3 dB, respectively. The full-path analog front-end shows a wide dynamic range of up to 77 dB in the measurement results.

Smaller hippocampal volume in APOE ε4 carriers independent of amyloid-ß (Aß) burden.

OBJECTIVE: To investigate the association of the APOE ε4 genotype with hippocampal volume, independent of Aß burden. METHOD: This cross-sectional study included 71 participants with mild cognitive impairment or mild AD. All participants were divided into carriers or non-carriers of the ε4 allele. The main outcome was hippocampal volume measured using structural magnetic resonance imaging; 18F-florbetaben positron emission tomography was additionally performed to investigate the association of APOE ε4 genotype with hippocampal volumes, independently of Aß burden. Analysis of covariance was conducted to compare the differences in hippocampal volumes between carriers and non-carriers of the ε4 allele after controlling for global Aß burden or local hippocampal Aß burden. RESULTS: The APOE ε4 genotype was associated with a smaller right and total hippocampal volume (right: 3160.16 ± 365.71 vs. 3365.24 ± 434.88, p < 0.05; total: 6257.48 ± 790.60 vs. 6599.52 ± 840.58, p < 0.05), independent of Aß burden. CONCLUSION: Our findings on the association of APOEε4 genotype with hippocampal volume independent of Aß burden suggest that the APOEε4 genotype may contribute to hippocampal neurodegeneration through an Aß-independent mechanism.

A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications.

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

2.4 GHz GaN HEMT Class-F Synchronous Rectifier Using an Independent Second Harmonic Tuning Circuit.

This paper proposes a class-F synchronous rectifier using an independent second harmonic tuning circuit for the power receiver of 2.4 GHz wireless power transmission systems. The synchronous rectifier can be designed by inverting the RF output port to the RF input port of the pre-designed class-F power amplifier based on time reversal duality. The design of the class-F power amplifier deploys an independent second harmonic tuning circuit in the matching networks to individually optimize the impedances of the fundamental and the second harmonic. The synchronous rectifier at the 2.4 GHz frequency is designed and implemented using a 6 W gallium nitride high electron mobility transistor (GaN HEMT). Peak RF-dc conversion efficiency of the rectifier of 69.6% is achieved with a dc output power of about 7.8 W, while the peak drain efficiency of the class-F power amplifier is 72.8%.

Psychometric Properties of Behavioral Checklist for Coping with Stress in Patients with Mood Disorders.

OBJECTIVE: Even though the importance of stress-coping, there is no reliable and valid scale to measure the stress-coping behavior yet. The purpose of this study is to explore the psychometric properties of Behavioral Checklist for Coping with Stress (BCCS). METHODS: A total of 458 subjects including healthy subjects and patients with bipolar or depressive disorders were analyzed. The reliability and validity of BCCS were examined by Chronbach's alpha and exploratory factor analysis using Principal Component Analysis. In order to evaluate criterion-related validity, the Pearson's correlation analyses between factors of BCCS and relevant scales were performed. RESULTS: BCCS showed good Chronobach's alpha (0.695-0.833) and had acceptable validity. Factor 1 and factor 4 of BCCS were negatively correlated with depression, anxiety and positivity correlated with task and problem-solving, avoidance, tension-releasing copings in common. Factor 2 and 3 were positively correlated with impulsivity, emotionality, avoidance, behavioral and verbal aggression and tension-releasing copings in common. Different from factor 2, factor 3 was positively correlated with depression, anxiety and anger-suppression. CONCLUSION: The results of this study suggest that this BCCS might be a reliable and valid scale for measuring stress-coping behaviors. This scale could facilitate research to investigate clinical implications related to behavioral stress-coping.