Real-Time Simulation of Passage-of-Time Encoding in Cerebellum Using a Scalable FPGA-Based System.

The cerebellum plays a critical role for sensorimotor control and learning. However, dysmetria or delays in movements' onsets consequent to damages in cerebellum cannot be cured completely at the moment. Neuroprosthesis is an emerging technology that can potentially substitute such motor control module in the brain. A pre-requisite for this to become practical is the capability to simulate the cerebellum model in real-time, with low timing distortion for proper interfacing with the biological system. In this paper, we present a frame-based network-on-chip (NoC) hardware architecture for implementing a bio-realistic cerebellum model with  âˆ¼ 100 000 neurons, which has been used for studying timing control or passage-of-time (POT) encoding mediated by the cerebellum. The simulation results verify that our implementation reproduces the POT representation by the cerebellum properly. Furthermore, our field-programmable gate array (FPGA)-based system demonstrates excellent computational speed that it can complete 1sec real world activities within 25.6 ms. It is also highly scalable such that it can maintain approximately the same computational speed even if the neuron number increases by one order of magnitude. Our design is shown to outperform three alternative approaches previously used for implementing spiking neural network model. Finally, we show a hardware electronic setup and illustrate how the silicon cerebellum can be adapted as a potential neuroprosthetic platform for future biological or clinical application.

A Survey of Wireless Sensor Network Based Air Pollution Monitoring Systems.

The air quality in urban areas is a major concern in modern cities due to significant impacts of air pollution on public health, global environment, and worldwide economy. Recent studies reveal the importance of micro-level pollution information, including human personal exposure and acute exposure to air pollutants. A real-time system with high spatio-temporal resolution is essential because of the limited data availability and non-scalability of conventional air pollution monitoring systems. Currently, researchers focus on the concept of The Next Generation Air Pollution Monitoring System (TNGAPMS) and have achieved significant breakthroughs by utilizing the advance sensing technologies, MicroElectroMechanical Systems (MEMS) and Wireless Sensor Network (WSN). However, there exist potential problems of these newly proposed systems, namely the lack of 3D data acquisition ability and the flexibility of the sensor network. In this paper, we classify the existing works into three categories as Static Sensor Network (SSN), Community Sensor Network (CSN) and Vehicle Sensor Network (VSN) based on the carriers of the sensors. Comprehensive reviews and comparisons among these three types of sensor networks were also performed. Last but not least, we discuss the limitations of the existing works and conclude the objectives that we want to achieve in future systems.

A scalable FPGA-based cerebellum for passage-of-time representation.

The cerebellum plays a critical role for sensorimotor control and learning. However dysmertria or delays in movements' onsets consequent to damages in cerebellum cannot be cured completely at the moment. To foster a potential cure based on neuroprosthetic technology, we present a frame-based Network-on-Chip (NoC) hardware architecture for implementing a bio-realistic cerebellum model with 100,000 neurons, which has been used for studying timing control or passage-of-time (POT) encoding mediated by the cerebellum. The results demonstrate that our implementation can reproduce the POT functionality properly. The computational speed can achieve to 25.6 ms for simulating 1 sec real world activities. Furthermore, we show a hardware electronic setup and illustrate how the silicon cerebellum can be adapted as a potential neuroprosthetic platform for future biological or clinical applications.

On-chip systolic networks for real-time tracking of pairwise correlations between neurons in a large-scale network.

The correlation map of neurons emerges as an important mathematical framework for a spectrum of applications including neural circuit modeling, neurologic disease bio-marking and neuroimaging. However, constructing a correlation map is computationally expensive, especially when the number of neurons is large. This paper proposes a hardware design using hierarchical systolic arrays to calculate pairwise correlations between neurons. Through mapping a computationally efficient algorithm for cross-correlation onto a massively parallel structure, the hardware is able to construct the correlation maps in a much shorter time. The proposed architecture was evaluated using a field programmable gate array. The results show that the computational delay of the hardware for constructing correlation maps increases linearly with the number of neurons, whereas the growth of delay is quadratic for a software-based serial approach. Also, the efficiency of our method for detecting abnormal behaviors of neural circuits is demonstrated by analyzing correlation maps of retinal neurons.

Stream-based Hebbian eigenfilter for real-time neuronal spike discrimination.

BACKGROUND: Principal component analysis (PCA) has been widely employed for automatic neuronal spike sorting. Calculating principal components (PCs) is computationally expensive, and requires complex numerical operations and large memory resources. Substantial hardware resources are therefore needed for hardware implementations of PCA. General Hebbian algorithm (GHA) has been proposed for calculating PCs of neuronal spikes in our previous work, which eliminates the needs of computationally expensive covariance analysis and eigenvalue decomposition in conventional PCA algorithms. However, large memory resources are still inherently required for storing a large volume of aligned spikes for training PCs. The large size memory will consume large hardware resources and contribute significant power dissipation, which make GHA difficult to be implemented in portable or implantable multi-channel recording micro-systems. METHOD: In this paper, we present a new algorithm for PCA-based spike sorting based on GHA, namely stream-based Hebbian eigenfilter, which eliminates the inherent memory requirements of GHA while keeping the accuracy of spike sorting by utilizing the pseudo-stationarity of neuronal spikes. Because of the reduction of large hardware storage requirements, the proposed algorithm can lead to ultra-low hardware resources and power consumption of hardware implementations, which is critical for the future multi-channel micro-systems. Both clinical and synthetic neural recording data sets were employed for evaluating the accuracy of the stream-based Hebbian eigenfilter. The performance of spike sorting using stream-based eigenfilter and the computational complexity of the eigenfilter were rigorously evaluated and compared with conventional PCA algorithms. Field programmable logic arrays (FPGAs) were employed to implement the proposed algorithm, evaluate the hardware implementations and demonstrate the reduction in both power consumption and hardware memories achieved by the streaming computing RESULTS AND DISCUSSION: Results demonstrate that the stream-based eigenfilter can achieve the same accuracy and is 10 times more computationally efficient when compared with conventional PCA algorithms. Hardware evaluations show that 90.3% logic resources, 95.1% power consumption and 86.8% computing latency can be reduced by the stream-based eigenfilter when compared with PCA hardware. By utilizing the streaming method, 92% memory resources and 67% power consumption can be saved when compared with the direct implementation of GHA. CONCLUSION: Stream-based Hebbian eigenfilter presents a novel approach to enable real-time spike sorting with reduced computational complexity and hardware costs. This new design can be further utilized for multi-channel neuro-physiological experiments or chronic implants.

Towards neuro-silicon interface using reconfigurable dynamic clamping.

Dynamic clamp emerges as an important apparatus to study the intrinsic neuronal properties through close-loop interactions between models and biological neurons. Modelling large-scale neuronal networks in software will result in significant computational delay that becomes a bottleneck to apply dynamic clamp for more complicated systems. In this paper, we present a real-time dynamic clamping system based on field programmable gate arrays (FPGAs) to accelerate the necessary computations. It also provides a flexible platform to reconfigure various model parameters and topologies. Realtime neuronal and synaptic models were implemented in FPGA, and interconnected with the stomatograstric ganglion (STG) nervous system to exemplify the real-time dynamics. Results show that our method can be effectively configured to mimic various biological neural networks and is two orders of magnitude faster than software approach using desktop computer.

Real-time neuronal networks reconstruction using hierarchical systolic arrays.

The correlation network of neurons emerges as an important mathematical framework for a spectrum of applications including neural modeling, brain disease prediction and brain-machine interface. However, construction of correlation network is computationally expensive, especially when the number of neurons is large and this prohibits realtime applications. This paper proposes a hardware architecture using hierarchical systolic arrays to reconstruct the correlation network. Through mapping an efficient algorithm for cross-correlation onto a massively parallel structure, the hardware can accomplish the network construction with extremely small delay. The proposed structure is evaluated using Field Programmable Gate Array (FPGA). Results show that our method is three orders of magnitudes faster than the software approach using desktop computer. This new method enables real-time network construction and leads to future novel devices of realtime neuronal network monitoring and rehabilitation.

Memory efficient on-line streaming for multichannel spike train analysis.

Rapid advances in multichannel neural signal recording technologies in recent years have spawned broad applications in neuro-prostheses and neuro-rehabilitation. The dramatic increase in data bandwidth and volume associated with multichannel recording requires a significant computational effort which presents major design challenges for brain-machine interface (BMI) system in terms of power dissipation and hardware area. In this paper, we present a streaming method for implementing real-time memory efficient neural signal processing hardware. This method exploits the pseudo-stationary property of neural signals and, thus, eliminates the need of temporal storage in batch-based processing. The proposed technique can significantly reduce memory size and dynamic power while effectively maintaining the accuracy of algorithms. The streaming kernel is robust when compared to the batch processing over a range of BMI benchmark algorithms. The advantages of the streaming kernel when implemented on field-programmable gate array (FPGA) devices are also demonstrated.

Feasibility study for future implantable neural-silicon interface devices.

The emerging neural-silicon interface devices bridge nerve systems with artificial systems and play a key role in neuro-prostheses and neuro-rehabilitation applications. Integrating neural signal collection, processing and transmission on a single device will make clinical applications more practical and feasible. This paper focuses on the wireless antenna part and real-time neural signal analysis part of implantable brain-machine interface (BMI) devices. We propose to use millimeter-wave for wireless connections between different areas of a brain. Various antenna, including microstrip patch, monopole antenna and substrate integrated waveguide antenna are considered for the intra-cortical proximity communication. A Hebbian eigenfilter based method is proposed for multi-channel neuronal spike sorting. Folding and parallel design techniques are employed to explore various structures and make a trade-off between area and power consumption. Field programmable logic arrays (FPGAs) are used to evaluate various structures.

A component-based FPGA design framework for neuronal ion channel dynamics simulations.

Neuron-machine interfaces such as dynamic clamp and brain-implantable neuroprosthetic devices require real-time simulations of neuronal ion channel dynamics. Field-programmable gate array (FPGA) has emerged as a high-speed digital platform ideal for such application-specific computations. We propose an efficient and flexible component-based FPGA design framework for neuronal ion channel dynamics simulations, which overcomes certain limitations of the recently proposed memory-based approach. A parallel processing strategy is used to minimize computational delay, and a hardware-efficient factoring approach for calculating exponential and division functions in neuronal ion channel models is used to conserve resource consumption. Performances of the various FPGA design approaches are compared theoretically and experimentally in corresponding implementations of the alpha-amino-3-hydroxy-5-methyl-4-isoxazole propionic acid (AMPA) and N-methyl-D-aspartate (NMDA) synaptic ion channel models. Our results suggest that the component-based design framework provides a more memory economic solution, as well as more efficient logic utilization for large word lengths, whereas the memory-based approach may be suitable for time-critical applications where a higher throughput rate is desired.

Equivalence-set genes partitioning using an evolutionary-DP approach.

Computation of transitive-closure equivalence sets has recently emerged as an important step for building static and dynamic models of gene network from DNA sequences. We present an evolutionary-DP approach in which dynamic programming (DP) is embedded into a genetic algorithm (GA) for fitness function evaluation of small equivalence sets (with m genes) within a large-scale genetic network of n genes, where n > m. This approach reduces a computation-intensive optimal problem of high dimension into a heuristic search problem on nCm candidates. The DP computation of transitive closure forms the basic fitness evaluation for selecting candidate chromosomes generated by GA operators. By introducing bounded mutation and conditioned crossover operators to constrain the feasible solution domain, small transitive-closure equivalence sets for large genetic networks can be found with much reduced computational effort. Empirical results have successfully demonstrated the feasibility of our GA-DP approach for offering highly efficient solutions to large scale equivalence gene-set partitioning problem. We also describe dedicated GA-DP hardware using field programmable gate arrays (FPGAs), in which significant speedup could be obtained over software implementation.