RESUMO
A foundational assumption of quantum error correction theory is that quantum gates can be scaled to large processors without exceeding the error-threshold for fault tolerance. Two major challenges that could become fundamental roadblocks are manufacturing high-performance quantum hardware and engineering a control system that can reach its performance limits. The control challenge of scaling quantum gates from small to large processors without degrading performance often maps to non-convex, high-constraint, and time-dynamic control optimization over an exponentially expanding configuration space. Here we report on a control optimization strategy that can scalably overcome the complexity of such problems. We demonstrate it by choreographing the frequency trajectories of 68 frequency-tunable superconducting qubits to execute single- and two-qubit gates while mitigating computational errors. When combined with a comprehensive model of physical errors across our processor, the strategy suppresses physical error rates by ~3.7× compared with the case of no optimization. Furthermore, it is projected to achieve a similar performance advantage on a distance-23 surface code logical qubit with 1057 physical qubits. Our control optimization strategy solves a generic scaling challenge in a way that can be adapted to a variety of quantum operations, algorithms, and computing architectures.
RESUMO
An amendment to this paper has been published and can be accessed via a link at the top of the paper.
RESUMO
Solid-state quantum coherent devices are quickly progressing. Superconducting circuits, for instance, have already been used to demonstrate prototype quantum processors comprising a few tens of quantum bits. This development also revealed that a major part of decoherence and energy loss in such devices originates from a bath of parasitic material defects. However, neither the microscopic structure of defects nor the mechanisms by which they emerge during sample fabrication are understood. Here, we present a technique to obtain information on locations of defects relative to the thin film edge of the qubit circuit. Resonance frequencies of defects are tuned by exposing the qubit sample to electric fields generated by electrodes surrounding the chip. By determining the defect's coupling strength to each electrode and comparing it to a simulation of the field distribution, we obtain the probability at which location and at which interface the defect resides. This method is applicable to already existing samples of various qubit types, without further on-chip design changes. It provides a valuable tool for improving the material quality and nano-fabrication procedures towards more coherent quantum circuits.
RESUMO
The promise of quantum computers is that certain computational tasks might be executed exponentially faster on a quantum processor than on a classical processor1. A fundamental challenge is to build a high-fidelity processor capable of running quantum algorithms in an exponentially large computational space. Here we report the use of a processor with programmable superconducting qubits2-7 to create quantum states on 53 qubits, corresponding to a computational state-space of dimension 253 (about 1016). Measurements from repeated experiments sample the resulting probability distribution, which we verify using classical simulations. Our Sycamore processor takes about 200 seconds to sample one instance of a quantum circuit a million times-our benchmarks currently indicate that the equivalent task for a state-of-the-art classical supercomputer would take approximately 10,000 years. This dramatic increase in speed compared to all known classical algorithms is an experimental realization of quantum supremacy8-14 for this specific computational task, heralding a much-anticipated computing paradigm.