The use of etched registration markers to make four-terminal electrical contacts to STM-patterned nanostructures.

We demonstrate the use of etched registration markers for the alignment of four-terminal ex situ macroscopic contacts created by conventional optical lithography to buried nanoscale Si:P devices, patterned by hydrogen-based scanning tunnelling microscope (STM) lithography. Using SiO(2) as a mask we are able to protect the silicon surface from contamination during marker fabrication and can achieve atomically flat surfaces with atomic-resolution imaging. The registration markers are shown to withstand substrate heating to approximately 1200 degrees C and epitaxial overgrowth of approximately 25 nm Si. Using a scanning electron microscope to position the STM tip with respect to the markers, we can achieve alignment accuracies of approximately 100 nm, which allows us to contact buried Si:P structures. We have applied this technique to fabricate P-doped wires of different widths and measured their I-V characteristics at 4 K, finding ohmic behaviour down to a width of approximately 27 nm.

Atomically precise placement of single dopants in si.

We demonstrate the controlled incorporation of P dopant atoms in Si(001), presenting a new path toward the creation of atomic-scale electronic devices. We present a detailed study of the interaction of PH3 with Si(001) and show that it is possible to thermally incorporate P atoms into Si(001) below the H-desorption temperature. Control over the precise spatial location at which P atoms are incorporated was achieved using STM H lithography. We demonstrate the positioning of single P atoms in Si with approximately 1 nm accuracy and the creation of nanometer wide lines of incorporated P atoms.

Progress in silicon-based quantum computing.

We review progress at the Australian Centre for Quantum Computer Technology towards the fabrication and demonstration of spin qubits and charge qubits based on phosphorus donor atoms embedded in intrinsic silicon. Fabrication is being pursued via two complementary pathways: a 'top-down' approach for near-term production of few-qubit demonstration devices and a 'bottom-up' approach for large-scale qubit arrays with sub-nanometre precision. The 'top-down' approach employs a low-energy (keV) ion beam to implant the phosphorus atoms. Single-atom control during implantation is achieved by monitoring on-chip detector electrodes, integrated within the device structure. In contrast, the 'bottom-up' approach uses scanning tunnelling microscope lithography and epitaxial silicon overgrowth to construct devices at an atomic scale. In both cases, surface electrodes control the qubit using voltage pulses, and dual single-electron transistors operating near the quantum limit provide fast read-out with spurious-signal rejection.