Single-crystalline ZnO sheet Source-Gated Transistors.

Due to their fabrication simplicity, fully compatible with low-cost large-area device assembly strategies, source-gated transistors (SGTs) have received significant research attention in the area of high-performance electronics over large area low-cost substrates. While usually based on either amorphous or polycrystalline silicon (α-Si and poly-Si, respectively) thin-film technologies, the present work demonstrate the assembly of SGTs based on single-crystalline ZnO sheet (ZS) with asymmetric ohmic drain and Schottky source contacts. Electrical transport studies of the fabricated devices show excellent field-effect transport behaviour with abrupt drain current saturation (IDS(SAT)) at low drain voltages well below 2 V, even at very large gate voltages. The performance of a ZS based SGT is compared with a similar device with ohmic source contacts. The ZS SGT is found to exhibit much higher intrinsic gain, comparable on/off ratio and low off currents in the sub-picoamp range. This approach of device assembly may form the technological basis for highly efficient low-power analog and digital electronics using ZnO and/or other semiconducting nanomaterial.

Solution processable multi-channel ZnO nanowire field-effect transistors with organic gate dielectric.

The present work focuses on nanowire (NW) applications as semiconducting elements in solution processable field-effect transistors (FETs) targeting large-area low-cost electronics. We address one of the main challenges related to NW deposition and alignment by using dielectrophoresis (DEP) to select multiple ZnO nanowires with the correct length, and to attract, orientate and position them in predefined substrate locations. High-performance top-gate ZnO NW FETs are demonstrated on glass substrates with organic gate dielectric layers and surround source-drain contacts. Such devices are hybrids, in which inorganic multiple single-crystal ZnO NWs and organic gate dielectric are synergic in a single system. Current-voltage (I-V) measurements of a representative hybrid device demonstrate excellent device performance with high on/off ratio of ~10(7), steep subthreshold swing (s-s) of ~400 mV/dec and high electron mobility of ~35 cm(2) V(-1) s(-1) in N2 ambient. Stable device operation is demonstrated after 3 months of air exposure, where similar device parameters are extracted including on/off ratio of ~4 × 10(6), s-s ~500 mV/dec and field-effect mobility of ~28 cm(2) V(-1) s(-1). These results demonstrate that DEP can be used to assemble multiples of NWs from solvent formulations to enable low-temperature hybrid transistor fabrication for large-area inexpensive electronics.