A Multilayer-Learning Current-Mode Neuromorphic System With Analog-Error Compensation.

Internet-of-things applications that use machine-learning algorithms have increased the demand for application-specific energy-efficient hardware that can perform both learning and inference tasks to adapt to endpoint users or environmental changes. This paper presents a multilayer-learning neuromorphic system with analog-based multiplier-accumulator (MAC), which can learn training data by stochastic gradient descent algorithm. As a component of the proposed system, a current-mode MAC processor, fabricated in 28-nm CMOS technology, performs both forward and backward processing in a crossbar structure of 500 × 500 6-b transposable SRAM arrays. The proposed system is verified in a two-layer neural network by using two prototype chips and an FPGA. Without any calibration circuit for the analog-based MAC, the proposed system compensates for non-idealities from analog operations by learning training data with the analog-based MAC. With 1-b (+1, 0, -1) batch update of 6-b synaptic weights, the proposed system achieves a recognition rate of 96.6% with a peak energy efficiency of 2.99 TOPS/W (1 OP = one unsigned 8-b × signed 6-b MAC operation) in the classification of the MNIST dataset.

An On-Chip Learning Neuromorphic Autoencoder With Current-Mode Transposable Memory Read and Virtual Lookup Table.

This paper presents an IC implementation of on-chip learning neuromorphic autoencoder unit in a form of rate-based spiking neural network. With a current-mode signaling scheme embedded in a 500 × 500 6b SRAM-based memory, the proposed architecture achieves simultaneous processing of multiplications and accumulations. In addition, a transposable memory read for both forward and backward propagations and a virtual lookup table are also proposed to perform an unsupervised learning of restricted Boltzmann machine. The IC is fabricated using 28-nm CMOS process and is verified in a three-layer network of encoder-decoder pair for training and recovery of images with two-dimensional pixels. With a dataset of 50 digits, the IC shows a normalized root mean square error of 0.078. Measured energy efficiencies are 4.46 pJ per synaptic operation for inference and 19.26 pJ per synaptic weight update for learning, respectively. The learning performance is also estimated by simulations if the proposed hardware architecture is extended to apply to a batch training of 60 000 MNIST datasets.

A Low-Power Wide Dynamic-Range Current Readout Circuit for Ion-Sensitive FET Sensors.

This paper presents an amplifier-less and digital-intensive current-to-digital converter for ion-sensitive FET sensors. Capacitance on the input node is utilized as a residue accumulator, and a clocked comparator is followed for quantization. Without any continuous-time feedback circuit, the converter performs a first-order noise shaping of the quantization error. In order to minimize static power consumption, the proposed circuit employs a single-ended current-steering digital-to-analog converter which flows only the same current as the input. By adopting a switching noise averaging algorithm, our dynamic element matching not only mitigates mismatch of current sources in the current-steering DAC, but also makes the effect of dynamic switching noise become an input-independent constant. The implemented circuit in 0.35 µm CMOS converts the current input with a range of 2.8 µ A to 15 b digital output in about 4 ms, showing a DNL of +0.24/-0.25 LSB and an INL of + 1.98/-1.98 LSB while consuming 16.8 µW.

A Single-Chip 64-Channel Ultrasound RX-Beamformer Including Analog Front-End and an LUT for Non-Uniform ADC-Sample-Clock Generation.

A 64-channel RX digital beamformer was implemented in a single chip for 3-D ultrasound medical imaging using 2-D phased-array transducers. The RX beamformer chip includes 64 analog front-end branches including 64 non-uniform sampling ADCs, a FIFO/Adder, and an on-chip look-up table (LUT). The LUT stores the information on the rising edge timing of the non-uniform ADC sampling clocks. To include the LUT inside the beamformer chip, the LUT size was reduced by around 240 times by approximating an ADC-sample-time profile w.r.t. focal points (FP) along a scanline (SL) for a channel into a piece-wise linear form. The maximum error between the approximated and accurate sample times of ADC is eight times the sample time resolution (Ts) that is 1/32 of the ultrasound signal period in this work. The non-uniform sampling reduces the FIFO size required for digital beamforming by around 20 times. By applying a 9-dot image from Field-II program and 2-D ultrasound phantom images to the fabricated RX beamformer chip, the original images were successfully reconstructed from the measured output. The chip in a 0.13-um CMOS occupies 30.25 [Formula: see text] and consumes 605 mW.

A single-chip 32-channel analog beamformer with 4-ns delay resolution and 768-ns maximum delay range for ultrasound medical imaging with a linear array transducer.

A single-chip 32-channel analog beamformer is proposed. It achieves a delay resolution of 4 ns and a maximum delay range of 768 ns. It has a focal-point based architecture, which consists of 7 sub-analog beamformers (sub-ABF). Each sub-ABF performs a RX focusing operation for a single focal point. Seven sub-ABFs perform a time-interleaving operation to achieve the maximum delay range of 768 ns. Phase interpolators are used in sub-ABFs to generate sampling clocks with the delay resolution of 4 ns from a low frequency system clock of 5 MHz. Each sub-ABF samples 32 echo signals at different times into sampling capacitors, which work as analog memory cells. The sampled 32 echo signals of each sub-ABF are originated from one target focal point at one instance. They are summed at one instance in a sub-ABF to perform the RX focusing for the target focal point. The proposed ABF chip has been fabricated in a 0.13- µ m CMOS process with an active area of 16 mm (2). The total power consumption is 287 mW. In measurement, the digital echo signals from a commercial ultrasound medical imaging machine were applied to the fabricated chip through commercial DAC chips. Due to the speed limitation of the DAC chips, the delay resolution was relaxed to 10 ns for the real-time measurement. A linear array transducer with no steering operation is used in this work.

An analog-digital hybrid RX beamformer chip with non-uniform sampling for ultrasound medical imaging with 2D CMUT array.

To reduce the memory area, a two-stage RX beamformer (BF) chip with 64 channels is proposed for the ultrasound medical imaging with a 2D CMUT array. The chip retrieved successfully two B-mode phantom images with a steering angle from -45 (°) to +45 (°), the maximum delay range of 8 µs, and the delay resolution of 6.25 ns. An analog-digital hybrid BF (HBF) is chosen for the proposed chip to utilize the easy beamforming operation in the digital domain and also to reduce chip area by minimizing the number of ADCs. The chip consists of eight analog beamformers (ABF) for the 1st-stage and a digital beamformer (DBF) for the 2nd-stage. The two-stage architecture reduces the memory area of both ABF and DBF by around four times. The DBF circuit is divided into three steps to further reduce the digital FIFO memory area by around twice. Coupled with the non-uniform sampling scheme, the proposed two-stage HBF chip reduces the total memory area by around 40 times compared to the uniform-sampling single-stage BF chip. The chip fabricated in a 0.13- µm CMOS process occupies the area of 19.4 mm(2), and dissipates 1.14 W with the analog supply of 3.3 V and the digital supply of 1.2 V.